Selective Gate Array Contacts for High-Density Transistors
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Solution Overview
Problem
Semiconductor devices face a conflict between establishing reliable electrical connections and minimizing 'dead areas' on wafers, as large connections consume valuable surface area, and existing solutions complicate design and increase resistance.
Innovation Solution
A semiconductor device design utilizing a double plug process with low-resistance material arrays and dielectric layers to enable selective contact between electrodes and connections, allowing for efficient distribution of transistor control signals and minimizing the use of metal tracks, thereby maximizing active area and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large electrical connections are used to ensure reliable connectivity, then connection reliability is improved, but wafer surface area is consumed reducing device density
Solution Approach 1:
The patent transitions from planar metal track routing to a vertical three-dimensional plug array structure. Multiple layers of plugs are stacked vertically to create electrical connections, moving the connection architecture from two-dimensional surface routing to three-dimensional vertical stacking, thereby freeing up wafer surface area while maintaining connection reliability
Solution Approach 2:
The electrical connection system is segmented into multiple discrete plug layers, where each layer contains a subset of plugs connecting to specific devices. This segmentation allows selective formation of connections in different layers, enabling reliable connectivity without requiring continuous large-area metal tracks across the wafer surface
2Reliability
If metal tracks are routed for gate connections, then electrical connectivity is established, but metal routing must be interrupted for other connections increasing resistance and complexity
Solution Approach 1:
The patent eliminates the need for interrupted metal tracks by forming vertical plug connections through dielectric layers. Each plug layer provides direct vertical access to underlying devices, removing the complexity of routing metal tracks across the wafer and eliminating the need to interrupt those tracks for other connections
Solution Approach 2:
Dielectric layers serve as intermediaries between the plug arrays and the semiconductor devices. The plugs are formed within these dielectric layers, which provide electrical isolation and mechanical support, enabling direct vertical connections without requiring complex metal track routing and interruptions
Data Source
AI summary
A semiconductor device may include a plurality of transistors, with a first array of low-resistance material formed in a first dielectric layer, with a gate subset of the first array formed on a plurality of gate electrodes of the transistors, and a source subset of the first array formed on a plurality of source regions of the transistors. A second array of low-resistance material may be formed in a second dielectric layer, with a gate subset of the second array formed on the gate subset of the first array and thereby electrically connected to the plurality of gate electrodes, and a source subset of the second array formed on the source subset of the first array and thereby electrically connected to the plurality of source regions.