Non-Planar Narrow-Channel Transistors for Cryogenic Drive Current
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Solution Overview
Problem
The challenge lies in manufacturing non-planar transistors with narrow channels that require precise control over dimensions and conductivity, particularly at very low temperatures to enhance carrier mobility and reduce leakage and contact resistance, while maintaining sufficient drive current.
Innovation Solution
The method involves forming non-planar transistor fins with ultra-thin, high-conductivity materials and using active-cooling structures to operate at very low temperatures, allowing for precise control of channel dimensions and conductivity, and integrating these transistors into integrated circuits with narrow-channel, non-planar architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If channel width is reduced to enable device scaling, then device density and switching speed improve, but drive current decreases
Solution Approach 1:
The patent transitions from planar (2D) channels to vertical/nanowire (3D) channels, adding a vertical dimension to the conduction path. This allows the channel to maintain a small lateral footprint while providing sufficient cross-sectional area for current flow through the vertical dimension, thus enabling device scaling without sacrificing drive current.
Solution Approach 2:
The patent employs composite material structures including high-k dielectric materials combined with metal gate materials, and core-shell nanowire structures with different semiconductor materials (e.g., Si core with Ge shell). These composite structures enable precise control of electrical properties while maintaining scaled dimensions, improving both drive current and device density.
2Power
If channel height is increased to improve sidewall conduction, then current density increases, but device control becomes more difficult
Solution Approach 1:
The patent segments the channel into multiple thin-film layers deposited sequentially, with each layer being precisely controllable in thickness. This segmentation approach allows the total channel height to be built up in controlled increments, maintaining manufacturing precision while achieving the desired height for improved sidewall conduction and current density.
Solution Approach 2:
The patent utilizes atomic layer deposition (ALD) and molecular beam epitaxy (MBE) techniques that enable precise control of film thickness at the nanometer and sub-nanometer scale. By changing deposition parameters such as precursor flow rates, temperature, and cycle numbers, the channel height can be precisely controlled to optimize sidewall conduction while maintaining manufacturing precision.
3Reliability
If very low temperatures are used to enhance carrier mobility and reduce leakage, then device performance improves, but system complexity and cooling requirements increase
Solution Approach 1:
The patent integrates the cooling system directly with the transistor structure by incorporating thermal management features at the device level, such as thermally conductive substrates and integrated heat sinks. This merging of cooling functionality into the device architecture itself reduces the need for separate, complex cooling systems while maintaining the low-temperature operation required for enhanced carrier mobility and reduced leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved conductivity, increased carrier mobility, reduced leakage, and sufficient drive current even at reduced channel widths, enhancing the performance of integrated circuits by maintaining them at cryogenic temperatures using active-cooling systems.
Implementation Method 1
integrated circuit die with non-planar transistors... using active-cooling systems
Data Source
AI summary
Narrow-channel, non-planar transistors and their manufacture on integrated circuit dies. A method includes forming channel portions of transistors from sidewall spacers by removing backbone features and coupling a gate structure, a source, and a drain to the channel portions. An integrated circuit die includes a gate structure, a source, and a drain coupled to pair-symmetric channel portions with sidewalls of differing heights. A method includes iteratively etching away portions of semiconductor material not covered by a mask or a passivation layer, revealing a channel portion by removing the mask and passivation layer, and coupling a gate structure, a source, and a drain to the channel portion. An integrated circuit die includes a gate structure, a source, and a drain coupled to a channel portion with vertically alternating, greater and lesser widths.