Dual-Gate NVM Structure with Shared Polysilicon Gates
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Solution Overview
Problem
The integration of non-volatile memory (NVM) devices with high and low voltage devices in semiconductor fabrication is challenging due to differing performance and operating requirements, leading to increased complexity and cost, particularly with reduced thermal budgets and thinner gate polysilicon and spacers, which affect breakdown voltages.
Innovation Solution
A method for forming a semiconductor structure with dual-gate NVM devices, high voltage, and low voltage devices on the same substrate, where gates for high voltage devices are formed simultaneously with select gates for NVM devices from a shared polysilicon layer, allowing for higher implant energy and annealing steps to improve breakdown voltage, while maintaining flexibility in device types and reducing process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If non-volatile memory devices are integrated with high voltage and low voltage devices using separate processing steps, then device functionality is achieved, but process complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the formation of high voltage device gates and non-volatile memory select gates into a single shared polysilicon layer that is patterned simultaneously for both device types. This merging of previously separate processing steps reduces process complexity and manufacturing cost while maintaining the ability to integrate multiple device functionalities on the same substrate.
Solution Approach 2:
The shared polysilicon layer serves multiple functions: it forms gates for high voltage devices and select gates for non-volatile memory devices simultaneously. This multi-functional approach allows a single processing sequence to accomplish what previously required separate steps, reducing overall process complexity while achieving versatile device integration.
2Productivity
If gate polysilicon and gate spacers are made thinner to meet scaling requirements, then device density improves, but breakdown voltage decreases
Solution Approach 1:
The patent applies different processing conditions to different regions of the shared polysilicon layer. By performing higher energy ion implantation and additional annealing steps specifically for the high voltage device gate regions, the patent locally enhances the electrical properties and breakdown voltage of high voltage devices without affecting the scaled dimensions needed for high device density.
Solution Approach 2:
The patent changes the processing parameters (implant energy and annealing temperature/time) for specific regions after the initial gate formation. This allows the same physical gate structure to achieve different electrical characteristics - higher breakdown voltage in high voltage device regions while maintaining thin dimensions for overall high device density.
3Reliability
If higher implant energy and annealing steps are applied to improve breakdown voltage, then high voltage device performance improves, but process complexity increases
Solution Approach 1:
The patent merges the additional higher energy implantation and annealing steps into the existing gate formation process sequence. By combining these complexity-reducing actions with the already-planned shared polysilicon layer patterning, the patent achieves improved breakdown voltage without adding separate, independent process steps.
Solution Approach 2:
The shared polysilicon layer structure serves dual purposes: it provides the gate structure for both high voltage and non-volatile memory devices, and simultaneously serves as the target for the higher energy implantation and annealing processes needed to improve breakdown voltage. The same structural element that enables integration also enables the reliability enhancement without requiring additional dedicated structures or processes.
Data Source
AI summary
A method for making a semiconductor structure includes forming an oxide layer onto non-volatile memory, high, and low voltage device regions of a substrate and forming a first gate material layer over the oxide layer. The first gate material layer is patterned to form a set of memory device select gates in the non-volatile memory device region and a set of gates in the high voltage device region. The patterning is performed while maintaining the oxide and first gate material layers over the low voltage device region. The method also includes forming a second gate material layer over the structure and forming a non-volatile storage layer between the set of select gates and the second gate material layer, from which a set of memory device control gates is patterned. Thereafter, the first gate material layer is patterned to form a set of gates in the low voltage device region.