Split-Gate Flash Memory With Extended Word Gate Below Channel
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Solution Overview
Problem
Conventional split-gate non-volatile memory devices face issues with poor program and erase performance, punchthrough, and trapped charge accumulation at sidewalls, limiting their efficiency and reliability.
Innovation Solution
The solution involves forming a band engineered or buried channel with an embedded word gate extending below the channel region, which reduces punchthrough and enhances program/erase speed by increasing the effective channel length and impact-ionization rate, while also avoiding trapped charges at sidewalls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the source and drain junctions are deep and at the same level to increase storage capacity, then the cell size is increased, but punchthrough susceptibility increases especially in narrow bandgap materials
Solution Approach 1:
The patent introduces a vertical dimension by extending the word gate below the channel region into the substrate. This three-dimensional configuration allows the word gate to provide electrostatic control over the channel from below, preventing punchthrough without requiring deeper source/drain junctions that would increase cell size. The vertical extension of the word gate creates a new spatial dimension for controlling carrier flow.
Solution Approach 2:
The patent applies different doping levels to different regions: light doping in the epitaxial layer for low control gate voltage operation, and heavy doping in the substrate for punchthrough prevention. This localized quality variation allows each region to optimize its function - the lightly-doped epitaxial layer provides good injection efficiency while the heavily-doped substrate region prevents punchthrough.
2Productivity
If the channel under the word gate is made narrow bandgap to improve injection efficiency, then program speed is improved, but punchthrough susceptibility increases
Solution Approach 1:
The patent uses a narrow bandgap material (such as SiGe) for the channel region under the word gate to enhance hot carrier injection efficiency and program speed. Simultaneously, the substrate region is heavily doped to provide punchthrough immunity. This local quality differentiation allows the channel to be optimized for speed while the substrate provides reliability protection.
Solution Approach 2:
By extending the word gate vertically into the substrate, the patent creates additional electrostatic control in the vertical dimension. This allows the narrow bandgap channel to operate at higher speeds without punchthrough, as the extended word gate provides stronger field control to prevent carrier leakage into the substrate.
3Quantity of substance
If trapped charges accumulate at sidewalls to increase charge storage, then memory capacity is improved, but program/erase speed decreases and performance fluctuations increase
Solution Approach 1:
The patent extracts or removes the problematic sidewall charge trapping layer from the conventional structure. By eliminating the sidewalls where trapped charges cause performance degradation, the patent achieves faster program/erase speeds and more consistent performance while maintaining adequate charge storage capacity through the control gate and floating gate structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves program and erase performance, reduces punchthrough, and enhances endurance by increasing the effective channel length and impact-ionization rate, thereby improving the overall efficiency and reliability of the memory devices.
Implementation Method 1
enhances program/erase speed by increasing the effective channel length and impact-ionization rate
Implementation Method 2
reduces punchthrough by enhancing punchthrough immunity
Data Source
AI summary
A split gate memory cell is fabricated with a word gate extending below an upper surface of a substrate having the channel region. An embodiment includes providing a band engineered channel with the word gate extending there through. Another embodiment includes forming a buried channel with the word gate extending below the buried channel.