Gate-All-Around HFET Structure for Sub-100 nm DIBL Control
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Solution Overview
Problem
Aggressively scaled semiconductor transistor devices with gate lengths less than 100 nm experience degraded output resistance and subthreshold turn-off slope due to drain-induced-barrier-lowering (dibl) in existing Planar Optoelectronic Technology (POET) structures.
Innovation Solution
The implementation of gate-all-around (GAA) layer structures for both NHFET and PHFET transistor devices, eliminating the back-gate region and using multiple quantum well structures to control charge carrier flow, with thin doped layers forming gate regions and implanted ions for contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-all-around (GAA) layer structures are implemented to eliminate the back-gate region, then output resistance and subthreshold turn-off slope are improved, but device complexity increases
Solution Approach 1:
The gate structure is segmented into multiple thin doped layers (first thin doped layer and second thin doped layer) that surround the quantum well structure on both top and bottom sides. This segmentation enables the gate to control charge carrier flow from multiple directions, eliminating the back-gate region and reducing drain-induced-barrier-lowering while maintaining manageable device complexity through systematic layering.
Solution Approach 2:
The gate control is extended from a single-plane configuration to a three-dimensional gate-all-around structure. The gate regions are positioned on both the top and bottom sides of the quantum well structure, creating vertical field effect that completely surrounds the channel. This dimensional change provides superior electrostatic control and eliminates the back-gate region, improving output resistance despite increased structural complexity.
2Reliability
If gate-all-around (GAA) layer structures are implemented with multiple quantum well structures, then transconductance is maximized, but manufacturing complexity increases
Solution Approach 1:
The active channel is segmented into multiple quantum well structures (first quantum well structure and second quantum well structure) positioned between the thin doped layers. Each quantum well contributes to the overall transconductance, and their stacked configuration allows systematic fabrication using standard molecular beam epitaxy processes, maximizing transconductance while maintaining ease of manufacture.
Solution Approach 2:
The device employs composite material structures combining different semiconductor layers with distinct doping types (n-type and p-type) and compositions. The quantum well structures are formed from compound semiconductor systems (such as GaAs/AlGaAs) with carefully engineered band structures, creating a composite material system that optimizes transconductance while being compatible with established manufacturing techniques.
3Reliability
If gate-all-around (GAA) layer structures are used with thin doped layers, then HFET capacitance is lowered, but manufacturing precision requirements increase
Solution Approach 1:
The gate is formed using thin doped layers (first thin doped layer and second thin doped layer) that are sufficiently thin to provide effective electrostatic control while minimizing parasitic capacitance. These thin films are deposited using molecular beam epitaxy with precise thickness control, achieving low HFET capacitance while meeting manufacturing precision requirements through advanced epitaxial growth techniques.
Solution Approach 2:
The doping concentration and thickness parameters of the thin doped layers are optimized to achieve the desired balance between electrostatic control and capacitance reduction. By carefully controlling the doping levels and layer thicknesses during epitaxial growth, the device achieves low HFET capacitance while remaining compatible with standard manufacturing precision capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces dibl, maximizes transconductance (gm), lowers HFET capacitance, and enables higher speed operation with optimized design parameters for both digital and analog optical devices, allowing scaling into the sub 100 nm range.
Implementation Method 1
The thin doped layers form gate regions that apply an electric field that controls the flow of charge carriers through the quantum well structures
Implementation Method 2
ions that are implanted with sufficient depth to penetrate through the GAA layer structure and contact the quantum well structures to form ion-implanted contact regions
Data Source
AI summary
Integrated circuitry is fabricated from semiconductor layers formed on a substrate, which include a p-type gate-all-around layer structure that includes a plurality of quantum well structures formed between a pair of p-type thin doped layers spaced vertically from one another. A p-type layer is formed above the p-type gate-all-around layer structure. An etch operation exposes the p-type layer. P-type ions are implanted into the exposed second p-type layer to a depth that extends through the p-type gate-all-around layer structure and contacts the p-type thin doped layers of the p-type gate-all-around layer structure. A gate electrode of an n-channel HFET device is formed in contact with the ion-implanted p-type region(s). Source and drain electrodes of the n-channel HFET device are formed in contact with ion-implanted n-type regions that contact the plurality of quantum well structures of the p-type gate-all-around layer structure. P-channel GAA HFET devices, complementary BICFET devices, stacked complementary HFET devices and circuits and/or logic gates based thereon, and a variety of optoelectronic devices and optical devices can also be formed as part of the integrated circuitry.