Backside Power Rail Contacts for Dense Cell Arrays With Lower Parasitics
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Solution Overview
Problem
Integrated circuits face challenges in achieving high integration density and performance due to increased parasitic elements from reduced wiring dimensions and power supply voltage, which affect operation speed and reliability.
Innovation Solution
Incorporating a backside power rail that provides power to a cell array through contacts extending from transistors, reducing parasitic components and enabling efficient power delivery and signal routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If wiring dimensions are reduced to increase integration density, then integration density is improved, but parasitic elements increase
Solution Approach 1:
The patent moves the power rail from the front side to the back side of the semiconductor structure, utilizing the third dimension (vertical stacking) to resolve the contradiction. This allows power delivery without occupying lateral wiring space, thereby maintaining high integration density while reducing parasitic effects in the signal paths.
Solution Approach 2:
The power delivery function is segmented from the signal routing function. By placing the power rail in a separate backside layer and using dedicated contact structures, the patent isolates power distribution from signal paths, reducing parasitic coupling while maintaining high integration density.
2Use of energy by moving object
If power supply voltage is reduced to decrease power consumption, then power consumption is reduced, but the influence of parasitic elements increases
Solution Approach 1:
By delivering power from the backside through dedicated vertical contacts, the patent creates low-impedance power paths that are electrically shorter and have reduced parasitic inductance. This allows lower operating voltages to be used effectively without the signal degradation that would normally result from parasitic elements.
3Object-affected harmful factors
If contacts are extended from source of transistor to backside power rail, then parasitic components are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent combines the contact structure with the existing transistor source region, using the same fabrication steps to form both. The contact extends vertically from the source through the interlayer dielectric to reach the backside power rail, integrating multiple functions into a single structural element that can be manufactured using standard semiconductor processing.
Data Source
Figure 1A
Figure 1B
Figure 2A
AI summary
An integrated circuit includes a cell array comprising a plurality of cells, each of the plurality of cells including at least one transistor, a power rail (PL1, PL2) in a power rail layer under the cell array, the power rail being configured to provide power to the cell array, and a plurality of contacts (BC1, BC2) between the cell array and the power rail. Each of the plurality of contacts extends downward from a source of a transistor of a corresponding one of the cells to the power rail.