SCR ESD Structure With Split Depletion Regions for Fast Turn-On
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Solution Overview
Problem
Existing semiconductor devices face a challenge in achieving both low capacitance and fast turn-on time simultaneously due to the conflicting requirements of depletion layer thickness, which affects the performance of silicon controlled rectifier (SCR) based ESD protection devices.
Innovation Solution
The semiconductor device incorporates two low capacitance regions in series, separated by an anti-punch region with higher doping, allowing for reduced turn-on time and maintaining low capacitance by utilizing a lowly doped epitaxial layer and strategically positioned space charge regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If a low doped region is made thick to achieve low capacitance, then capacitance decreases, but turn-on time increases
Solution Approach 1:
The patent divides the single low doped region into two separate low doped regions (first and second n- or p- regions) separated by a high doped anti-punch layer. Each region forms its own space charge region, creating two depletion layers in series. This segmentation allows each depletion layer to be thinner than a single thick depletion layer would need to be, reducing the nonlinear turn-on time dependency while maintaining low total capacitance through the series combination.
Solution Approach 2:
The patent applies different doping levels to different regions: low doping in the n- or p- regions to create thick depletion layers for low capacitance, and high doping in the anti-punch layer to prevent carrier injection and punch-through. This local differentiation of doping quality enables each region to optimize its function - the low doped regions for capacitance control and the high doped anti-punch layer for switching speed and punch-through prevention.
2Shape
If a single low doped region is used for low capacitance, then capacitance decreases, but punch-through occurs
Solution Approach 1:
The high doped anti-punch layer acts as an intermediary barrier between the two low doped regions. This intermediate high doped region prevents direct carrier injection from one low doped region to the other, blocking the punch-through pathway while allowing the depletion layers to extend into the low doped regions for capacitance control.
3Speed
If the low doped region is made thin for fast switching, then turn-on time decreases, but capacitance increases
Solution Approach 1:
By segmenting the depletion path into two thinner depletion layers separated by the anti-punch layer, each layer can be made thin enough for fast switching while the series combination maintains low total capacitance. The total depletion width is distributed across two regions rather than concentrated in one thick region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the semiconductor device to achieve low capacitance and fast switching times, suppressing punch-through and maintaining low leakage, thereby enhancing the overall performance of the SCR based ESD protection device.
Implementation Method 1
The p− region will be depleted and it will give a low capacitance due to the depletion layer
Data Source
AI summary
A semiconductor device is provided that includes a first n+ region, a first p+ region within the first n+ region, a second n+ region, a second p+ region, positioned between the first n+ region and the second n+ region. The first n+ region, the second n+ region and the second p+ region are positioned within a p− region. A first space charge region and a second space charge region are formed within the p− region. The first space region is positioned between the first n+ region and the second p+ region, and the second space region is positioned between the second p+ region and the second n+ region.