6T SRAM Cell Shared Contact Plugs for Compact Layout
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Solution Overview
Problem
Current six transistor static random access memory (6T SRAM) cell designs face challenges in achieving a compact size and optimal contact-to-poly process window while maximizing memory density within limited chip area.
Innovation Solution
The design incorporates a first and second inverter structure with shared contact plugs connecting gate and drain regions of transistors, allowing for a compact layout and additional metal routing under the first metal layer, thereby reducing cell size and improving the contact-to-poly process window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional 6T SRAM cell layout is used, then transistor connectivity is achieved, but cell area is large and memory density is limited
Solution Approach 1:
The patent merges the contact plugs for connecting transistor gates and drains into shared contact structures. Specifically, a first shared contact plug connects the gate of the second pull-up transistor with the drains of the first pull-up and first pull-down transistors, while a second shared contact plug connects the gate of the first pull-up transistor with the drains of the second pull-up and second pull-down transistors. This merging of multiple connections into shared contacts reduces the total area required for interconnections, thereby reducing cell area and improving memory density.
2Productivity
If compact cell design is implemented, then memory density increases, but contact-to-poly process window deteriorates
Solution Approach 1:
The shared contact plugs combine multiple electrical connections (gate and drain contacts) into unified structures that are larger in dimension. This merging approach creates contact structures with sufficient area to maintain good electrical connection during fabrication processes, thereby preserving an adequate contact-to-poly process window even as the overall cell size is reduced for higher memory density.
3Adaptability or versatility
If additional metal routing is added under M1 layer, then routing flexibility improves, but process complexity increases
Solution Approach 1:
The patent utilizes the space under the first metal (M1) layer to route additional metal interconnections. By employing this unused dimensional space, the design achieves improved routing flexibility and connectivity without adding lateral complexity to the existing metal layers. This vertical utilization of routing space allows for more flexible circuit design while avoiding the need for additional metal layers or complex via structures.
Data Source
AI summary
A 6T SRAM cell includes a substrate having thereon a first pull-up (PU-1) transistor, a first pull-down (PD-1) transistor, a second pull-up (PU-2) transistor, and a second pull-down (PD-2) transistor. A first contact hard mask partially overlaps with a source diffusion region of the PU-1 transistor. A second contact hard mask partially overlaps with a first gate and a source diffusion region of the PD-1 transistor. A first contact plug partially lands on the first contact hard mask and partially lands on the source diffusion region of the PU-1 transistor. A second contact plug partially lands on the second contact hard mask and partially lands on the source diffusion region of the PD-1 transistor.