3D Protrusion Field-Effect Transistor for Smaller Chip Footprint
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Solution Overview
Problem
The semiconductor industry faces challenges in increasing the areal density of integrated circuits due to the limitations in miniaturizing transistors, as thin film transistors (TFTs) have a large areal footprint, making them unsuitable for routing and detrimental to chip area scaling.
Innovation Solution
The development of protrusion field-effect transistors with dielectric protrusions that extend from the substrate, allowing for a three-dimensional channel structure, which reduces the effective channel width and length, thereby increasing the transistor's efficiency and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If thin film transistors are used for BEOL integration, then low temperature processing is achieved, but large areal footprint is incurred
Solution Approach 1:
The patent transitions from planar 2D channel structure to three-dimensional protrusion structures ( fins, nanowires, or nanosheets) extending vertically from the substrate. This dimensional change allows the channel to occupy vertical space rather than only horizontal plane, thereby reducing the areal footprint while maintaining effective channel area for current conduction. The protrusions extend into the interlayer dielectric, utilizing the third dimension to pack more transistor functionality into a smaller chip area.
2Ease of manufacture
If planar TFT structure is used, then simple fabrication is achieved, but large chip area is required
Solution Approach 1:
The invention introduces vertical protrusion structures that extend from the substrate surface into the overlying dielectric layers. This three-dimensional configuration increases the effective channel width and area without proportionally increasing the planar footprint, thereby achieving higher transistor density and reduced chip area requirement while remaining compatible with existing fabrication processes.
Solution Approach 2:
The protrusion structures are formed within and extend into the interlayer dielectric regions, effectively nesting the channel structure within the existing BEOL architecture. The protrusions occupy vertical space within the dielectric layers rather than requiring additional horizontal space, allowing the transistor to be integrated within the existing chip structure without expanding the overall chip footprint.
3Area of stationary object
If transistor size is reduced to increase areal density, then chip area scaling is improved, but transistor performance deteriorates
Solution Approach 1:
By forming vertical protrusions with height extending into the dielectric, the effective channel area is increased without increasing the planar dimensions. This allows the transistor to maintain adequate drive current and performance characteristics even when the lateral footprint is reduced for higher density integration. The three-dimensional channel provides sufficient conduction path area to compensate for the reduced planar size.
Solution Approach 2:
The protrusion structures utilize composite material stacks including semiconductor materials (e.g., III-V compounds, oxide semiconductors) combined with high-k dielectric materials and metal gates. This composite structure enables enhanced carrier mobility and drive current in the vertical channel, maintaining transistor performance while reducing the planar footprint for higher density integration.
Data Source
AI summary
A transistor, an integrated semiconductor device, and methods of making the same are provided. The transistor includes a dielectric layer having a plurality of dielectric protrusions, a channel layer conformally covering the protrusions of the dielectric layer to form a plurality of trenches between two adjacent dielectric protrusion, a gate layer disposed on the channel layer. The gate layer 106 has a plurality of gate protrusions fitted into the trenches. The transistor also includes active regions aside the gate layer. The active regions are electrically connected to the channel layer.