High-K Gate Dielectric Width Layout for Overlap Capacitance Control
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Solution Overview
Problem
Increasing direct current and radio frequency performance in integrated circuits by enhancing overlap capacitance leads to increased threshold voltage variability due to substrate doping and drive-in temperature increases.
Innovation Solution
A structure and method involving transistors on a substrate with different high dielectric constant (high-K) gate dielectrics, where the gate body and high-K gate dielectric have different widths in various regions, allowing for controlled overlap capacitance without increasing dopants or drive-in annealing temperature, achieved through masking and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If doping of the substrate is increased to achieve increased overlap capacitance, then the overlap capacitance is improved, but the threshold voltage variability increases
Solution Approach 1:
The patent applies local quality by creating different high-K gate dielectric widths in different regions of the substrate. First regions have a first high-K gate dielectric width while second regions have a second high-K gate dielectric width, allowing each region to be optimized for its specific function. This enables increased overlap capacitance in specific regions without uniformly increasing doping across the entire substrate, thereby avoiding increased threshold voltage variability.
Solution Approach 2:
The patent changes the physical parameter of gate dielectric width to control electrical characteristics. By varying the high-K gate dielectric width between different regions, the patent achieves different capacitance values without changing doping concentrations. This parameter change allows optimization of overlap capacitance while maintaining stable threshold voltage characteristics.
2Stress or pressure
If different high-K gate dielectric widths are used in different regions, then overlap capacitance is improved without increasing doping, but the device complexity increases
Solution Approach 1:
The patent segments the substrate into first regions and second regions with different high-K gate dielectric widths. This segmentation allows independent optimization of each region's electrical characteristics. The segmentation is implemented through a fabrication process that forms different width high-K gate dielectrics in different regions, enabling customized capacitance values for different transistor types or functions on the same chip.
Solution Approach 2:
Different regions are assigned different gate dielectric widths based on their specific functional requirements. First regions may use a larger width for high capacitance applications while second regions use a smaller width for low capacitance applications. This local quality approach optimizes each region's performance without unnecessarily complicating other regions.
Data Source
AI summary
A structure and method of forming different high dielectric constant (high-K) gate dielectrics for different transistors on the same substrate, are disclosed. A first region includes a first transistor(s) on the substrate having a first gate structure having a first gate body over a first high-K gate dielectric. The first gate body and the first high-K gate dielectric have different widths defining a first width difference. A second region includes a second transistor(s) on the substrate having a second gate structure having a second gate body over a second high-K gate dielectric. The second gate body and the second high-K gate dielectric have different widths defining a second width difference. The first width difference is different than the second width difference, i.e., amongst transistors in the different regions. The different gate dielectric widths improve control of overlap capacitance of the transistors without increasing dopants or an annealing temperature.