Cryogenic SRAM Cell Layout for Higher Density and Lower RC Delay
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Solution Overview
Problem
Current SRAM technologies face challenges in increasing density while maintaining performance, as scaling dimensions or using fewer transistors can lead to compromised drive current and increased parasitic capacitance, resulting in poor RC delay products.
Innovation Solution
Implementing a microprocessor with a 6T SRAM cell design that operates at cryogenic temperatures using stacked nanosheet transistors, which reduces leakage currents and enhances drive currents, and integrating 4T SRAM cells with active cooling systems to maintain low temperatures, thereby improving SRAM density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the dimensions of lines and spaces in an SRAM cell are scaled down to increase density, then SRAM density is improved, but drive current decreases and parasitic capacitance increases causing RC delay products to worsen
Solution Approach 1:
The patent changes the temperature parameter to cryogenic conditions (below -25°C, preferably below -50°C or -70°C) to fundamentally alter the electrical characteristics of the SRAM cell. This temperature parameter change reduces parasitic effects and enables the use of fewer transistors while maintaining or improving performance metrics like drive current and RC delay products
Solution Approach 2:
The patent replaces the conventional approach of scaling physical dimensions (mechanical scaling) with a thermal field-based solution. Instead of making transistors smaller, the invention uses cryogenic cooling to achieve the same density improvement while maintaining electrical performance through temperature-dependent physical effects
2Quantity of substance
If fewer than six transistors are used in an SRAM cell to increase density, then SRAM density is improved, but leakage currents increase and compromise SRAM performance
Solution Approach 1:
The patent changes the temperature parameter to cryogenic conditions where the physical properties of semiconductors fundamentally change. At these temperatures, thermal generation of carriers is suppressed, leading to dramatically reduced leakage currents that enable fewer-transistor cell designs to achieve both high density and low leakage simultaneously
Solution Approach 2:
The patent exploits the phase transition of the semiconductor material from room-temperature behavior to cryogenic behavior, where carrier generation mechanisms change fundamentally. This phase-like transition in material properties at low temperatures enables the suppression of leakage currents while maintaining functional operation
3Quantity of substance
If conventional SRAM cell designs are used without cooling systems, then device complexity is reduced, but SRAM performance and density cannot be improved beyond scaling limitations
Solution Approach 1:
The patent integrates multiple functions into the cooling system: temperature control for performance optimization, leakage current suppression, and enabling of fewer-transistor designs. The cooling infrastructure serves as a platform that simultaneously addresses multiple performance metrics rather than requiring separate solutions for each challenge
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a substantial boost in SRAM performance and density by leveraging cryogenic temperatures to reduce leakage and parasitic resistances, enabling higher drive currents and lower voltage operation, with an approximate 2.5× improvement in SRAM density for 4T cells compared to 6T cells without performance loss.
Implementation Method 1
operates at cryogenic temperatures using stacked nanosheet transistors, which reduces leakage currents and enhances drive currents
Implementation Method 2
integrating 4T SRAM cells with active cooling systems to maintain low temperatures
Data Source
AI summary
Integrated circuits including static random-access memory (SRAM) bit-cells that are actively cooled to a low temperature (e.g., in the cryogenic range) where transistor drive currents become significantly increased and transistor leakage currents significantly reduced. With the drive current improvement, bit-cell capacitance may be reduced by defining narrower transistor fin structures and/or four transistor (4T) bit-cells may be implemented, for example with two parallel transistor fins and colinear gate electrodes.