Memory Device Isolation Structure for AA-Clipping Defect Reduction

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Solution Overview

Problem

Current memory devices face defects such as AA-clipping during fabrication, leading to leakage paths and performance degradation due to the reduction in device size, which is not effectively addressed by existing technologies.

Innovation Solution

A memory device design featuring an isolation structure higher than the second active region, with a recessing process to expose sidewalls of the upper portion of the isolation structure, and an oxide cap surrounding the protruding isolation structure, reducing defects and improving performance by minimizing over-etching and AA-clipping damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If device size is reduced to increase component density, then component density is improved, but device performance deteriorates due to AA-clipping defects and leakage paths

Engineering Contradiction:
Improvecomponent densityVSAvoiddevice performance
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent introduces a vertical dimension by forming an isolation structure that protrudes from the substrate surface at a height of 5-50 nm. This vertical protrusion creates a physical barrier in the third dimension (height) to prevent lateral etching damage, thereby solving the AA-clipping problem that arises from planar scaling.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The isolation structure acts as an intermediary element between adjacent memory cells. It provides a protective barrier that mediates the etching process, preventing direct contact between etching tools and the active region corners, thus eliminating leakage paths while maintaining device scaling.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If conventional fabrication processes are used for scaled devices, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to AA-clipping defects

Engineering Contradiction:
Improvefabrication simplicityVSAvoidactive region integrity
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The isolation structure is formed before the etching process that defines the active regions. This preliminary structural preparation ensures that when subsequent etching occurs, the isolation structure is already in place to protect the active region corners from AA-clipping damage.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The isolation structure provides localized protection specifically at the corners of active regions where AA-clipping occurs. The protruding structure (5-50 nm height) creates a local geometric feature that prevents etching tool damage to critical areas while leaving other regions unaffected.

Inventive Principle:
Principle #3Local quality

3Reliability

If isolation structure height is increased to protect active regions, then active region protection is improved, but device complexity increases

Engineering Contradiction:
Improveactive region protectionVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent specifies a precise height parameter range of 5-50 nm for the isolation structure protrusion. This parameter optimization provides sufficient protection against AA-clipping while minimizing the increase in structural complexity and maintaining compatibility with existing fabrication processes.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20170200724A1Memory device and fabricating method thereof
Publication Date: 2017.07.13 MICRON TECHNOLOGY INC
  • US20170200724A1 patent drawing
  • US20170200724A1 patent drawing
  • US20170200724A1 patent drawing

AI summary

A memory device and a method for fabricating the same are provided. The memory device includes a substrate and an isolation structure. The substrate has at least two memory cells, and each of the memory cells includes a first active region, a second active region, and a gate structure. The first active region and the second active region are alternately disposed in the substrate. The gate structure is disposed in the substrate and between the first active region and the second active region. The isolation structure is disposed between and protruding from the second active regions of two adjacent memory cells.