Vertical Fin Gate Structure With Capping Layer for Threshold Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices has led to challenges in enhancing the operating characteristics of planar MOSFETs due to their reduced size, necessitating the development of MOSFETs with three-dimensional channel structures.
Innovation Solution
A semiconductor device is designed with a vertical active region, fin structures, and a gate structure that includes alternating semiconductor layers and a capping layer, where the gate structure overlaps the fin structure and source/drain regions, improving electrical characteristics by preventing direct contact between the gate dielectric and the semiconductor layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the gate dielectric is placed in direct contact with the semiconductor layers to simplify the structure, then the device complexity is reduced, but the reliability of the gate dielectric deteriorates due to direct contact causing abnormal threshold voltage changes
Solution Approach 1:
A semiconductor capping layer is introduced as an intermediary component between the gate dielectric and the alternating semiconductor layers. This capping layer prevents direct contact between the gate dielectric and the semiconductor layers, thereby maintaining gate dielectric reliability and preventing abnormal threshold voltage changes while preserving structural simplicity.
2Productivity
If the planar MOSFET size is reduced to increase integration density, then the productivity is improved, but the operating characteristics deteriorate due to size reduction limitations
Solution Approach 1:
The patent transitions from a planar two-dimensional MOSFET structure to a three-dimensional vertical structure by stacking alternating semiconductor layers with different bandgaps in the vertical direction. This dimensional change enables continued scaling and increased integration density while maintaining or improving operating characteristics through the vertical channel configuration and enhanced carrier control.
3Volume of moving object
If the alternating semiconductor layers are stacked closely to reduce device height, then the volume is reduced, but the manufacturing precision requirements increase due to the need to prevent direct contact between gate dielectric and semiconductor layers
Solution Approach 1:
The semiconductor capping layer serves as a buffer and alignment reference layer between the gate dielectric and the alternating semiconductor layers. This intermediary layer provides a well-defined interface that simplifies the manufacturing process and reduces precision requirements for aligning the gate dielectric with the underlying semiconductor structures, enabling close stacking while maintaining manufacturing feasibility.
Data Source
AI summary
A semiconductor device includes an active region extending from a substrate in a vertical direction, source/drain regions spaced apart from each other on the active region, a fin structure between the source/drain regions on the active region, the fin structure including a lower semiconductor region on the active region, a stack structure having alternating first and second semiconductor layers on the lower semiconductor region, a side surface of at least one of the first semiconductor layers being recessed, and a semiconductor capping layer on the stack structure, an isolation layer covering a side surface of the active region, a gate structure overlapping the fin structure and covering upper and side surfaces of the fin structure, the semiconductor capping layer being between the gate structure and each of the lower semiconductor region and stack structure, and contact plugs electrically connected to the source/drain regions.