Floating-Gate Memory Fabrication Without Plasma Etching Damage

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Solution Overview

Problem

High-density plasma reactive-ion etching in semiconductor manufacturing causes plasma damage, adversely affecting device reliability and data storage in advanced semiconductor processes.

Innovation Solution

A manufacturing method that avoids reactive-ion etching by forming floating and control gates using polysilicon and metal gates respectively, with a process involving sacrificial patterns, dielectric layers, and planarization, eliminating the need for high-density plasma etching and reducing charge trap.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If high-density plasma reactive-ion etching is used to define patterns for floating gates, then manufacturing precision is improved, but device reliability deteriorates due to plasma damage and charge traps

Engineering Contradiction:
Improvepattern definition precisionVSAvoiddevice reliability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent divides the gate formation process into multiple stages: first forming sacrificial patterns, then depositing dielectric layers, and finally removing sacrificial materials to create floating gates. This segmented approach replaces single-step plasma etching with a multi-step process that avoids plasma damage while maintaining precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by first depositing sacrificial materials and dielectric layers before forming the actual gate structures. The sacrificial patterns are prepared in advance, and dielectric layers are deposited beforehand to protect against plasma damage during subsequent processing steps.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If high-density plasma reactive-ion etching is used in advanced semiconductor processes, then manufacturing capability is improved, but data storage reliability deteriorates

Engineering Contradiction:
Improvemanufacturing capabilityVSAvoiddata storage reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces dielectric layers as intermediary protective barriers between the plasma environment and the gate structures. These dielectric layers act as mediators that allow plasma processing to proceed while preventing direct plasma damage to the sensitive gate regions, thus maintaining productivity while protecting data storage reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If conventional gate formation processes are used, then manufacturing simplicity is maintained, but plasma damage occurs affecting device performance

Engineering Contradiction:
Improveprocess simplicityVSAvoidplasma damage
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent applies beforehand cushioning by depositing dielectric layers and sacrificial materials before plasma processing steps. These protective layers cushion the gate structures against plasma damage, preventing harmful effects while allowing the manufacturing process to proceed with minimal complexity increase.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Improves device reliability and enables the formation of low-power semiconductor devices by preventing plasma damage and allowing for direct formation of metal control gates over floating gates.

Implementation Method 1

A tunneling dielectric layer is formed on a surface of the substrate exposed in the openings

Methodology Applied
Scientific EffectQuantum tunneling:

Implementation Method 2

The polysilicon is planarized to form the plurality of floating gates on the tunneling dielectric layer

Methodology Applied
Scientific EffectChemical mechanical polishing:

Implementation Method 3

an ONO layer is conformally deposited on the surface of the floating gates, an inner surface of the trenches, and a surface of the second inner dielectric layer

Methodology Applied
Scientific EffectConformal deposition:

Data Source

PatentUS11785769B2Manufacturing method of semiconductor device including floating gate and control gate
Publication Date: 2023.10.10 WINBOND ELECTRONICS CORP
  • US11785769B2 patent drawing
  • US11785769B2 patent drawing
  • US11785769B2 patent drawing

AI summary

A manufacturing method of semiconductor device is provided. In the manufacturing method, a tunneling dielectric layer, floating gates on the tunneling dielectric layer, an ONO layer on the floating gates, and control gates on the ONO layer are formed. During the formation of the floating gates and the control gates, reactive-ion etching (R.I.E.) is not used at all, and thus damage to the floating and control gates from high-density plasma is prevented, such as charge trap in the floating gates may be significantly reduced to improve the reliability of data storage.