Terminal Interconnect Pillar Structures for Low-Resistance IC Scaling
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Solution Overview
Problem
As integrated circuits (ICs) continue to scale down, the challenge lies in scaling down the footprint of terminal interconnects while maintaining effective electrical connectivity, as conventional interconnect structures face difficulties in patterning and filling due to tapered via openings and increased resistance.
Innovation Solution
The implementation of device terminal interconnect structures featuring pillar or ridge architectures, which allow for a reduced footprint and improved connectivity by patterning conductive materials into pillars or ridges that can be further contacted by upper-level interconnects, potentially replacing conventional conductive vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional conductive via structures are used, then electrical connectivity is achieved, but the footprint cannot be sufficiently reduced due to tapered via openings and high aspect ratios
Solution Approach 1:
The patent transitions from conventional via structures (vertical holes) to pillar structures that extend laterally in addition to vertically. This dimensional change allows the interconnect to achieve both small footprint and manufacturable aspect ratios by distributing the conductive path across multiple dimensions rather than concentrating it in a single vertical hole.
Solution Approach 2:
The interconnect structure is segmented into multiple conductive regions including pillars, ridges, and upper-level interconnects. This segmentation allows each component to be optimized independently - pillars provide vertical connectivity with reduced aspect ratios, while lateral extensions reduce the overall footprint without requiring extremely narrow via openings.
2Area of moving object
If lateral diameter of conductive via is reduced to minimize footprint, then area is reduced, but resistance increases and patterning becomes more challenging
Solution Approach 1:
Instead of reducing the via diameter in a single dimension, the patent extends the conductive path laterally to create pillars and ridges. This distributes the resistance across a larger total conductive volume while maintaining a small footprint, effectively reducing resistance without requiring larger via openings.
Solution Approach 2:
The interconnect structure combines multiple conductive materials and configurations (pillars, ridges, upper-level interconnects) to achieve optimal electrical properties. This composite approach allows the structure to maintain low resistance through increased conductive volume while keeping the footprint small, avoiding the need to reduce via diameter to extreme dimensions.
3Ease of manufacture
If conventional via structures are used, then manufacturing process is established, but aspect ratio is high making filling more difficult
Solution Approach 1:
The patent introduces lateral dimensions to the conductive structure, creating pillars and ridges that extend horizontally. This dimensional change reduces the effective aspect ratio of each conductive element by providing alternative pathways for current flow, making the filling process more manageable while maintaining overall vertical connectivity.
Solution Approach 2:
The high aspect ratio vertical via is segmented into multiple lower aspect ratio components (pillars and ridges). Each segmented element has a more manageable aspect ratio that is easier to fill using conventional processes, while the collective structure maintains the necessary vertical electrical connectivity.
Data Source
AI summary
Integrated circuit structures including device terminal interconnect pillar structures, and fabrication techniques to form such structures. Following embodiments herein, a small transistor terminal interconnect footprint may be achieved by patterning recesses in a gate interconnect material and/or a source or drain interconnect material. A dielectric deposited over the gate interconnect material and/or source or drain interconnect material may be planarized to expose portions of the gate interconnect material and/or drain interconnect material that were protected from the recess patterning. An upper level interconnect structure, such as a conductive line or via, may contact the exposed portion of the gate and/or source or drain interconnect material.