Gate Air Spacer Sizing to Prevent Isolation Region Collapse
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Solution Overview
Problem
Conventional methods for forming air spacers in semiconductor devices face challenges, particularly in high aspect ratio situations, where air spacers are difficult to form and gate structures over isolation regions tend to collapse during the fabrication process.
Innovation Solution
The formation of a highly etchable liner next to gate spacers in specific regions and selective doping of dielectric gate spacers to enhance etching selectivity and control air spacer dimensions, allowing for efficient formation of air spacers with tunable sizes and reduced risk of gate structure collapse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to form air spacers, then manufacturing simplicity is maintained, but air spacer formation becomes difficult in high aspect ratio situations and gate structures may collapse
Solution Approach 1:
A sacrificial liner layer is introduced as an intermediary material between the gate spacer and the air spacer cavity. This liner layer has high etch selectivity, allowing it to be removed easily after defining the air spacer region, thereby enabling air spacer formation in high aspect ratio structures without causing gate collapse. The liner acts as a temporary structural support and etching guide during the fabrication process.
Solution Approach 2:
The sacrificial liner layer is formed preliminarily before the air spacer is created. This preliminary structure defines the air spacer footprint and provides etch selectivity, allowing subsequent etching processes to form the air spacer cavity without directly attacking the gate structure. The liner is removed after serving its purpose, leaving a clean air spacer interface.
2Reliability
If air spacer size is increased to reduce capacitance, then device performance improves, but manufacturing control becomes more difficult
Solution Approach 1:
The etch selectivity parameter between the sacrificial liner layer and surrounding materials is optimized to enable precise control of air spacer dimensions. By adjusting the liner material composition and thickness, the etching process can be tuned to remove the liner completely while leaving adjacent structures intact, thereby achieving well-defined air spacer sizes that can be scaled according to device requirements.
Solution Approach 2:
Physical contact-based dimension control is replaced by etch chemistry-based control. Instead of relying on mechanical masking or physical constraints to define air spacer boundaries, the invention uses selective etching chemistry to remove the sacrificial liner only in desired regions, providing superior dimensional control and flexibility in air spacer sizing.
3Manufacturing precision
If selective doping is applied to enhance etching selectivity, then air spacer formation precision improves, but process complexity increases
Solution Approach 1:
Selective doping is applied locally to specific regions of the gate spacer structure where enhanced etching resistance is needed. Rather than uniformly doping the entire structure, the process targets only the portions that require dimensional control during air spacer formation. This localized approach achieves precise air spacer definition while minimizing the overall process complexity and material usage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach facilitates the formation of air spacers with optimized dimensions, improving device performance by reducing capacitance and preventing gate structure collapse, while allowing for flexible tuning of air spacer sizes to suit different device regions.
Implementation Method 1
performing one or more etching processes forms a first air spacer in the first device region by removing the liner and the second dielectric spacer
Implementation Method 2
Selective doping of dielectric gate spacers to enhance etching selectivity and control air spacer dimensions
Data Source
AI summary
A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.