Fringeless FET Gate Layout for High-Density Multi-Voltage Circuits
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Solution Overview
Problem
Providing field effect transistors that operate at different operating voltages at a high device density is a challenge in semiconductor devices.
Innovation Solution
A semiconductor structure comprising multiple field effect transistors with specific gate electrode and trench isolation structures, and a method of forming these transistors involving multiple semiconductor material layers and dielectric layers to achieve high density and efficient operation across varying voltage ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple field effect transistors with different operating voltages are integrated to increase device density, then device density is improved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The gate electrode is segmented into two distinct portions: a first gate electrode portion extending over the first active region and a second gate electrode portion extending over the second active region. This segmentation allows each portion to be independently optimized for its respective transistor's operating voltage requirements while maintaining a unified gate structure, thereby increasing device density without proportionally increasing manufacturing complexity
Solution Approach 2:
The common gate structure serves multiple functions by simultaneously controlling both the first field effect transistor operating at a first voltage and the second field effect transistor operating at a second voltage. This multi-functional design enables high-density integration of transistors with different operating voltages using a shared gate formation process, reducing the overall manufacturing complexity despite the diversity in transistor requirements
2Productivity
If transistors with different operating voltages are integrated at high density, then device density is improved, but process feasibility and manufacturing ease deteriorate
Solution Approach 1:
The first gate electrode portion and second gate electrode portion are merged into a single continuous gate electrode structure formed through a unified deposition and patterning process. This merging approach allows both transistors with different operating voltages to be manufactured simultaneously using the same process steps, significantly improving manufacturing feasibility while achieving high device density
Solution Approach 2:
Different regions of the gate electrode are assigned different local qualities: the first gate electrode portion is optimized for the first operating voltage with specific material composition and thickness, while the second gate electrode portion is optimized for the second operating voltage. This local optimization within a unified structure enables high-density integration of multi-voltage transistors using standard manufacturing processes
Data Source
AI summary
A lateral extent of a gate electrode of a field effect transistor along a gate electrode direction that is perpendicular to a channel direction can be the same as a width of an underlying active region. A gate electrode of an additional field effect transistor may extend over a trench isolation structure that laterally surrounds the additional field effect transistor. Different types of electrodes may be formed by patterning a lower gate material layer and by patterning an upper gate material layer with different patterns such that patterned portions of the lower gate material layer are confined within areas of active regions, while patterned portions of the upper gate material layer extends outside of the areas of the active regions.