Junction-less MOS Transistor Vertical Structure Heat Dissipation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor technologies advance, there is a need for new techniques to maintain the performance of MOS transistors as they are scaled down, and existing MOS transistors face challenges in manufacturing complexity and power dissipation.
Innovation Solution
The development of junction-less MOS transistors with a bulk semiconductor region, where the channel region, drain, and source regions share the same polarity and doping concentration, simplifying the manufacturing process and improving current handling capability by eliminating accumulation regions and enhancing heat dissipation through a vertical structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional MOS transistors are scaled down to maintain performance, then integration density improves, but manufacturing complexity and power dissipation increase
Solution Approach 1:
The patent extracts and eliminates the accumulation region from the transistor structure, transitioning to a junction-less design where the channel region has the same doping concentration as drain and source regions. This removal of the accumulation region simplifies the manufacturing process by reducing the number of doping steps and process complexity while maintaining scaled-down performance.
Solution Approach 2:
Instead of the conventional approach where drain and source regions have different doping concentrations than the channel, the patent inverts this by making the channel region have the same doping concentration as the drain and source regions. This inversion creates a junction-less structure that simplifies manufacturing while enabling continued scaling.
2Productivity
If conventional MOS transistors are scaled down, then integration density improves, but power dissipation increases
Solution Approach 1:
By extracting and removing the accumulation region from the transistor structure, the patent eliminates the primary source of power dissipation in conventional scaled transistors. The junction-less design reduces parasitic capacitances and resistances, thereby reducing power dissipation while maintaining high integration density.
3Temperature
If junction-less MOS transistors use vertical structure, then heat dissipation improves, but device structure becomes more complex
Solution Approach 1:
The patent transitions from a planar horizontal structure to a vertical structure where the channel extends in the vertical dimension. This dimensional change improves heat dissipation by providing a direct thermal path from the active region to the substrate, while the vertical configuration actually simplifies the overall device architecture by eliminating the need for complex accumulation region formation.
4Ease of manufacture
If junction-less MOS transistors eliminate accumulation regions, then manufacturing simplicity improves, but current handling capability must be maintained
Solution Approach 1:
The patent changes the doping concentration parameter to be uniform across the channel, drain, and source regions, eliminating the need for complex multi-step doping processes. To maintain current handling capability, the patent optimizes other parameters such as channel dimensions, gate voltage, and material composition, compensating for the simplified doping structure.
Data Source
AI summary
A MOS transistor structure comprises a substrate including a bulk semiconductor region, a first gate formed in a first trench, a first drain/source region, a second drain/source region, wherein the first drain/source region and the second drain/source region are formed on opposing sides of the first gate. The MOS transistor structure further comprises a second gate formed in a second trench, a third drain/source region, wherein the third drain/source region and the second drain/source region are formed on opposing sides of the second gate and a channel region formed in the bulk semiconductor region, wherein the channel region, the first drain/source region, the second drain/source region and the third drain source region share a same polarity.


