Oxide Semiconductor Structure With CAAC Alignment for High On-State Current
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high on-state current, high frequency characteristics, reliability, scalability, and low power consumption while maintaining favorable electrical characteristics and design flexibility.
Innovation Solution
A semiconductor device is designed with a conductor, insulators, and an oxide layer where the oxide includes regions with aligned c-axes of crystals, and specific roughness parameters are maintained to enhance planarity and crystallinity, allowing for improved transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional semiconductor materials and structures are used, then manufacturing processes are well-established, but on-state current and frequency characteristics are limited
Solution Approach 1:
The patent changes the physical and chemical parameters of the semiconductor layer by controlling the crystallinity and crystal orientation (c-axis alignment) of the oxide semiconductor. This allows achieving high on-state current while maintaining stable frequency characteristics through precise parameter control during film formation
Solution Approach 2:
The patent uses composite structure combining oxide semiconductor with specific crystalline properties and conventional semiconductor materials. The oxide semiconductor layer with aligned c-axes provides high mobility, while the overall device structure integrates with conventional components to ensure reliability
2Power
If oxide semiconductor with CAAC structure is used, then on-state current increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary actions during the film formation process by pre-setting the deposition conditions (temperature, pressure, gas flow) to promote spontaneous formation of CAAC structure. The substrate is prepared and heated in advance to facilitate proper crystal nucleation and growth without requiring post-processing
Solution Approach 2:
The oxide semiconductor film forms the CAAC structure through self-organization during deposition. The atoms automatically arrange themselves into c-axis aligned crystalline regions without external intervention or complex processing steps, reducing manufacturing precision requirements
3Productivity
If device scaling is pursued, then integration density increases, but maintaining electrical characteristics becomes difficult
Solution Approach 1:
The patent utilizes the ability to precisely control film thickness, composition, and crystallinity parameters of the oxide semiconductor layer. Even as device dimensions are scaled down, these parameters can be adjusted to maintain the necessary electrical characteristics and performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables semiconductor devices with high on-state current, reliable high-frequency operation, and reduced power consumption, while allowing for scalability and flexible design.
Implementation Method 1
a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline) structure, which are neither single crystal nor amorphous, have been found in an oxide semiconductor
Implementation Method 2
For example, a sputtering method may be used to form the insulator 224 and the insulator 250
Data Source
AI summary
A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a conductor, a first insulator in contact with a side surface of the conductor, a second insulator in contact with a top surface of the conductor and a top surface of the first insulator, and an oxide over the second insulator. The oxide includes a region that overlaps with the conductor with the second insulator interposed therebetween. The maximum height of a roughness curve (Rz) of the top surface of the conductor is 6.0 nm or smaller. The region includes crystals, and c-axes of the crystals are aligned in the normal direction of the top surface of the conductor.