T-Gate NMOS Channel Stressing via Prestressed Layer Relaxation
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Solution Overview
Problem
Existing methods for improving electron mobility in NMOS transistors, such as using strained substrates and stress-memorization technologies, are not optimized for applying voltage stress effectively, leading to inefficiencies and performance limitations, especially when trying to enhance both NMOS and PMOS transistors simultaneously.
Innovation Solution
A method involving the formation of a pre-stressed layer with compressive stress, followed by the modification of source and drain regions to elastically release this stress and induce tension in the conduction channel, allowing for direct application of stress close to the channel, thereby increasing electron mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If stress is applied indirectly through source and drain regions using a stress liner, then tensile stress is induced in the channel, but stress loss occurs due to the indirect mechanism
Solution Approach 1:
The patent extracts the stress application mechanism from the indirect source-and-drain route and applies it directly to the channel region through the stress liner. By removing the intermediate transmission steps through source and drain regions, the patent achieves more efficient stress transfer with minimal loss, as the stress liner is positioned to actuate stress directly on the channel.
Solution Approach 2:
The stress liner acts as a new intermediary element that provides a more efficient stress transfer path compared to the traditional source-and-drain mediation. The stress liner is specifically designed and positioned to mediate stress transfer directly to the channel, reducing stress loss by eliminating the indirect transmission path through source and drain regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively applies stress to the conduction channel, enhancing electron mobility and preventing structural defects from reaching the channel, resulting in improved performance for NMOS transistors without degrading PMOS performance.
Implementation Method 1
the modification of the source and drain regions is configured to elastically release the compressive stress from a portion of the prestressed layer located below the conduction channel, so as to apply the tensile stress state in the conduction channel
Implementation Method 2
it is the elastic relaxation of the prestressed layer that leads to tensioning of the conduction channel
Data Source
Figure 1A~1C
Figure 1D~1E
Figure 1F~1G
AI summary
The invention relates to a method for making a microelectronic device comprising the following steps: - forming a grid pattern on the substrate, above a conduction channel, - forming spacers defining source and drain regions, - modifying the source and drain regions to generate a tensile stress in the conduction channel; advantageously, the method comprises: - before forming the grid pattern, forming a compression prestressed layer on the substrate, - forming an active layer on the prestressed layer, said active layer being intended to accommodate the conduction channel; advantageously, the modification of the source and drain regions is configured to elastically release the compression stress of the prestressed layer, so as to apply the tensile stress state in the channel.