Trench Semiconductor Substrate Grooves to Suppress Warpage

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Solution Overview

Problem

Semiconductor devices with trench gate structures face challenges in substrate warpage during manufacturing, which affects the yield and resistance of the drift layer, making it difficult to achieve high yield and efficient power conversion.

Innovation Solution

The semiconductor device incorporates a groove on the substrate surface with specific dimensions and orientations to reduce warpage, formed using plasma etching techniques, which helps in thinning the substrate while maintaining structural integrity and reducing resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the substrate is thinned to reduce resistance of the drift layer, then the resistance decreases and power conversion efficiency improves, but substrate warpage occurs during manufacturing reducing yield

Engineering Contradiction:
Improvesubstrate flatnessVSAvoidmanufacturing yield
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The substrate surface is segmented by forming grooves that divide the continuous surface into separated regions. These grooves act as stress relief structures that prevent warpage while maintaining the necessary substrate thinning for low resistance. The segmentation approach allows the substrate to be thinned without compromising overall flatness.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of uniformly treating the entire substrate surface, grooves are strategically formed in specific locations where stress concentration occurs. This local modification approach addresses warpage issues in critical areas while preserving the overall substrate integrity and electrical performance.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If grooves are formed on the substrate surface to suppress warpage, then substrate flatness improves, but additional manufacturing steps are required increasing process complexity

Engineering Contradiction:
Improvesubstrate flatnessVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The groove formation process is merged with existing substrate processing steps. By integrating groove formation into the standard manufacturing flow, the additional process complexity is minimized while achieving the desired substrate flatness improvement.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively suppresses substrate warpage and reduces the resistance of the drift layer, enabling the production of semiconductor devices with high yield and improved power conversion capabilities.

Implementation Method 1

formed using plasma etching techniques

Methodology Applied
Scientific EffectPlasma etching: Plasma

Data Source

PatentUS11990544B2Semiconductor device
Publication Date: 2024.05.21 KK TOSHIBA
  • US11990544B2 patent drawing
  • US11990544B2 patent drawing
  • US11990544B2 patent drawing

AI summary

A semiconductor device according to an embodiment includes: a first electrode; and a substrate including a first surface in contact with the first electrode and a second surface provided opposite to the first surface, the first surface including a first groove including a first length and a second length shorter than the first length, the first length in a first direction parallel to the first surface, the second length in a second direction parallel to the first surface, the second direction intersecting with the first direction, wherein the substrate includes a semiconductor layer having first conductive type, a first semiconductor region provided between the semiconductor layer and the second surface, the first semiconductor region having second conductive type, a second semiconductor region provided between the first semiconductor region and the second surface, the second semiconductor region having first conductive type higher than an impurity concentration of the semiconductor layer, and a second electrode provided in a first trench, the second electrode being provided opposite to the first semiconductor region via a first insulating film, the first trench reaching the semiconductor layer from the second surface, the first trench extending in the second direction.