Vertical Channel Memory Structure With Air Gaps for Coupling Noise

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Solution Overview

Problem

Current semiconductor memory devices face challenges in achieving high integration density and improved electrical characteristics, particularly with vertical channel transistors, due to issues like interference and coupling noise between adjacent active pillars and word lines.

Innovation Solution

The semiconductor memory device incorporates alternating active pillars with vertical and horizontal portions, separated by insulating layers that include air gaps to reduce coupling noise and enhance electrical characteristics, and a method of fabricating these devices involves forming air gaps in specific positions within the insulating layers to optimize dielectric properties.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If vertical channel transistors are used to increase integration density, then the integration density improves, but coupling noise and interference between adjacent active pillars and word lines increase

Engineering Contradiction:
Improveintegration densityVSAvoidcoupling noise and interference
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

An insulating layer is introduced as an intermediary substance between adjacent active pillars and between word lines. This insulating layer acts as a mediator that reduces coupling noise and interference while allowing the vertical channel transistor structure to maintain its high integration density benefits.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

Air gaps are extracted and introduced into the insulating layer to further reduce coupling noise. By removing material (creating voids) in specific regions of the insulating layer, the harmful electromagnetic coupling between adjacent structures is minimized while preserving the overall device architecture.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If air gaps are introduced in insulating layers to reduce coupling noise, then electrical characteristics improve, but device complexity increases

Engineering Contradiction:
Improveelectrical characteristicsVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The insulating layer is designed with a porous structure containing air gaps. This approach improves electrical characteristics by reducing coupling noise through the use of low-dielectric-constant material (air), while the porous structure is integrated into the existing fabrication process flow.

Inventive Principle:
Principle #31Porous materials

Solution Approach 2:

The dielectric constant parameter of the insulating layer is changed by introducing air gaps. This parameter modification reduces electromagnetic coupling between adjacent structures, improving electrical characteristics. The complexity is managed by controlling the size, shape, and distribution of air gaps through standard lithography and etching processes.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration increases integration density and improves electrical characteristics by reducing interference and coupling noise, leading to better performance and efficiency in semiconductor memory devices.

Implementation Method 1

a first insulating layer between the first and second word lines... the first insulating layer may include a first air gap between the first side surface and the second side surface

Methodology Applied
Scientific EffectDielectric isolation: Dielectric

Data Source

PatentEP4373234A1Semiconductor memory device
Publication Date: 2024.05.22 SAMSUNG ELECTRONICS CO LTD
  • EP4373234A1 patent drawingFigure 1
  • EP4373234A1 patent drawingFigure 2
  • EP4373234A1 patent drawingFigure 3

AI summary

A semiconductor memory device includes a bit line on a substrate and extending in a first direction, first and second active pillars on the bit line, the first active pillar including a first horizontal portion coupled to the bit line and a first vertical portion extending from the first horizontal portion, the second active pillar including a second horizontal portion coupled to the bit line and a second vertical portion extending from the second horizontal portion. First and second word lines are on the first and second horizontal portions of the first and second active pillars, respectively, and extend in a second direction crossing the first direction. A first insulating layer is between the first and second word lines. A first and second side surfaces of the first and second horizontal portions face each other. The first insulating layer includes an air gap between the first and second side surfaces.