Thin-Barrier Contact Plug Structure for Low-Resistance Scaling
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Solution Overview
Problem
As the aspect ratio of contact plugs in semiconductor devices increases and their diameter decreases, it becomes challenging to maintain low resistance, which is essential for effective connectivity between source/drain layers and upper wiring.
Innovation Solution
The semiconductor device incorporates a contact plug structure with a conductive metal structure and a barrier pattern where the barrier pattern's thickness is less than or equal to 10 Å, and the metal's grain diameter ranges from 8 nm to 15 nm, ensuring low resistance by minimizing grain size and barrier volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the aspect ratio of contact plugs increases and diameter decreases, then device scaling is achieved, but resistance increases
Solution Approach 1:
The patent changes the physical parameters of the contact plug by reducing grain size to 8-15 nm and controlling barrier pattern thickness to ≤10 Å, which fundamentally alters the electrical properties to achieve low resistance despite high aspect ratio and small diameter
Solution Approach 2:
The contact plug uses a composite structure combining metal grains embedded in a dielectric matrix with an ultra-thin barrier pattern, creating a composite material system that achieves both mechanical stability and low electrical resistance
2Reliability
If barrier pattern thickness is reduced, then resistance decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent specifies a precise parameter range for barrier pattern thickness (≤10 Å) that balances electrical performance with manufacturability, achieving low resistance while maintaining fabrication feasibility
3Reliability
If metal grain size is reduced, then resistance decreases, but manufacturing complexity increases
Solution Approach 1:
The patent reduces metal grain size to 8-15 nm to decrease resistance by increasing the number of conduction paths, while using specific fabrication processes to manage the complexity of grain structure control
Data Source
AI summary
A semiconductor device includes: an active fin disposed on a substrate and protruding from an upper surface of the substrate; a gate structure disposed on the active fin; a source/drain layer disposed on a portion of the active fin adjacent to the gate structure; an ohmic contact pattern on the source/drain layer; and a contact plug disposed on an upper surface of the ohmic contact pattern, wherein the contact plug includes: a conductive structure including a metal; and a barrier pattern covering a lower surface and a sidewall of the conductive structure, wherein a thickness of the barrier pattern is equal to or less than about 10 Å, and wherein a maximum diameter of a grain of the metal included in the conductive structure is in a range of about 8 nn to about 15 nm.