3D Transistor Capacitor Cell Interconnects for Higher Capacitance
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Solution Overview
Problem
Semiconductor integrated circuit devices using three-dimensional transistor devices face challenges in implementing a capacitor cell with a large capacitance value per unit area, which affects noise resistance and performance due to high-speed frequency and low operating voltage.
Innovation Solution
The design includes a capacitor cell with a three-dimensional transistor device, featuring longer local interconnects that protrude from the diffusion layer to increase parasitic capacitance, and the use of double patterning to form metal interconnects at extremely small intervals, allowing for a larger capacitance value per unit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If local interconnects are made longer to increase parasitic capacitance, then capacitance value per unit area is improved, but interconnect length and cell area increase
Solution Approach 1:
The patent utilizes the vertical dimension by extending local interconnects in the second direction (perpendicular to the fin direction) to protrude from the diffusion layer. This three-dimensional interconnect arrangement increases parasitic capacitance without proportionally increasing the planar footprint, effectively resolving the contradiction between capacitance value and area occupation.
2Quantity of substance
If double patterning is used to form metal interconnects at small intervals, then capacitance density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies double patterning to divide the metal interconnect formation into two separate exposure processes using different masks. This segmentation allows adjacent interconnects to be formed at extremely small intervals that would be impossible with single-patterning, thereby increasing capacitance density while managing manufacturing complexity through systematic process division.
3Speed
If high-speed frequency and low operating voltage are used to improve performance, then operating speed is improved, but noise resistance deteriorates
Solution Approach 1:
The patent converts the harmful effect of high-speed operation (increased noise susceptibility) into a benefit by intentionally increasing parasitic capacitance through extended local interconnects. This additional capacitance acts as a decoupling effect that stabilizes power supply voltage and filters noise, thereby improving noise resistance while maintaining high-speed operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the performance of semiconductor integrated circuit devices by increasing capacitance values, improving noise resistance and overall performance.
Implementation Method 1
A length of a portion, of the second local interconnect, which protrudes from the second three-dimensional diffusion layer in a direction away from the power supply interconnect in the second standard cell is greater than a length of a portion, of the first local interconnect, which protrudes from the first three-dimensional diffusion layer in a direction away from the power supply interconnect in the first standard cell. In other words, in the capacitor cell, the local interconnect connected to the three-dimensional diffusion layer of the three-dimensional transistor device has a long portion extending from the three-dimensional diffusion layer. This feature increases the parasitic capacitance between the local interconnect and the gate interconnect
Data Source
AI summary
The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.