Backside Gate Tie-Down Structure for Nanowire Gate Cut Scaling
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Solution Overview
Problem
The scaling of multi-gate and nanowire transistors in integrated circuits poses challenges due to constraints on lithographic processes, particularly in maintaining critical dimension and spacing, leading to device variability and complexity in manufacturing.
Innovation Solution
The implementation of a backside gate tie-down structure and process, which includes a metal gate cut approach after gate dielectric and work function metal deposition, allowing for seamless work function metal deposition and reducing device variation by simplifying manufacturing and improving metal fill capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate and nanowire transistors are scaled down to below 10 nanometer node, then device density and functional unit capacity are improved, but maintaining mobility improvement and short channel control becomes increasingly difficult
Solution Approach 1:
The patent transitions from planar 2D gate control to three-dimensional multi-gate structures (tri-gate, gate-all-around) that wrap around the channel in multiple dimensions. This dimensional change provides enhanced electrostatic control over the channel, improving short channel control while maintaining small footprint for high density.
Solution Approach 2:
The patent implements nested gate structures where gates are wrapped around the channel in multiple layers (e.g., gate-all-around enclosing the channel completely). This nesting provides multi-directional control of the channel, enhancing mobility and short channel control without increasing device area.
2Productivity
If the number of fundamental building blocks is increased in a given region, then device capacity is improved, but constraints on lithographic processes become overwhelming
Solution Approach 1:
The patent divides the gate structure into multiple discrete segments (e.g., separate gates for different channels in nanowire devices). This segmentation allows independent optimization of each unit while maintaining overall high density, and simplifies lithographic patterning compared to continuous structures.
Solution Approach 2:
By moving to vertical and three-dimensional gate configurations, the patent increases device capacity in the vertical dimension rather than only lateral expansion. This reduces the lithographic burden on the planar dimension while maintaining high device density.
3Manufacturing precision
If there is a trade-off between critical dimension and spacing in lithographic patterning, then feature size control is improved, but device density is reduced
Solution Approach 1:
The patent resolves the spacing-critical dimension trade-off by utilizing vertical and three-dimensional space for device structures. Gates wrap around channels in multiple dimensions, allowing tight lateral spacing while maintaining functional dimensions through vertical extension, thereby achieving high density without sacrificing critical dimension control.
Solution Approach 2:
Nested gate structures enclose channels in multiple layers, effectively using vertical space to increase device functionality without increasing lateral footprint. This nesting allows critical dimensions to be controlled in the lateral plane while density is increased through vertical stacking.
Data Source
AI summary
Integrated circuit structures having backside gate tie-down are described. In an example, a structure includes a first vertical stack of horizontal nanowires over a first sub-fin, and a second vertical stack of horizontal nanowires over a second sub-fin, the second vertical stack of horizontal nanowires spaced apart from and parallel with the first vertical stack of horizontal nanowires. A gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, wherein the first gate structure extends along an entirety of the first sub-fin. A second gate structure portion is over the second vertical stack of horizontal nanowires, wherein the second gate structure does not extend along an entirety of the second sub-fin. A gate cut is between the first gate structure portion and the second gate structure portion.