Angled Via Etching for Semiconductor Contact Alignment
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Solution Overview
Problem
The fabrication of conductive contacts to semiconductor devices, particularly in flash EEPROM memory cells, faces challenges such as misaligned contacts and complex integration schemes due to the decreasing size of integrated circuit devices, leading to reduced device yield and increased complexity in patterning and etching processes.
Innovation Solution
A method involving the formation of a gate stack and impurity doped regions within a semiconductor substrate, followed by the deposition of a dielectric layer and etching of a via with a major axis oriented at an angle greater than zero and no greater than 90 degrees, allowing for the formation of a conductive contact that minimizes misalignment and optimizes contact size and position relative to adjacent gate stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional contact fabrication methods are used with decreasing device size, then device density increases, but manufacturing precision deteriorates due to misaligned contacts
Solution Approach 1:
The patent rotates the via major axis from the conventional orientation (parallel to gate stacks) to a new orientation at an angle of 0-90 degrees relative to the gate stacks. This dimensional change in orientation allows the via to be positioned more precisely relative to the impurity doped region while maintaining proper spacing from adjacent gate stacks, thereby improving contact alignment precision as devices scale to higher densities
Solution Approach 2:
The patent changes the orientation parameter of the via major axis from the conventional alignment (parallel to gate stacks, 0 degrees) to a new angular range (0-90 degrees relative to gate stacks). This parameter change optimizes the via positioning to achieve better alignment with the impurity doped region while avoiding adjacent gate stacks, resolving the alignment precision issue at scaled device dimensions
2Quantity of substance
If conventional contact fabrication methods are used, then device density can be increased, but device complexity increases due to complex integration schemes for patterning and etching
Solution Approach 1:
The patent modifies the via orientation parameter to an angle of 0-90 degrees relative to the gate stacks, which simplifies the patterning and etching processes by optimizing the via alignment with the impurity doped region. This parameter change reduces the complexity of integration schemes while enabling increased device density
3Manufacturing precision
If via orientation is optimized at an angle of 0-90 degrees from gate stacks, then manufacturing precision improves for contact alignment, but device complexity increases due to non-conventional etching requirements
Solution Approach 1:
The patent specifies a via major axis orientation at an angle of 0-90 degrees relative to the gate stacks, which optimizes contact alignment precision with the impurity doped region. While this non-conventional orientation may require adjusted etching parameters, it eliminates the need for complex overlay and masking steps, resulting in net reduced process complexity
Data Source
AI summary
Methods for fabricating semiconductor structures and contacts to semiconductor structures are provided. A method comprises providing a substrate and forming a gate stack on the substrate. The gate stack is formed having a first axis. An impurity doped region is formed within the substrate adjacent to the gate stack and a dielectric layer is deposited overlying the impurity doped region. A via is etched through the dielectric layer to the impurity doped region. The via has a major axis and a minor axis that is perpendicular to and shorter than the major axis. The via is etched such that the major axis is disposed at an angle greater than zero and no greater than 90 degrees from the first axis. A conductive contact is formed within the via.