Oxide TFT Trench Gate Structure for Short-Channel Control
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Solution Overview
Problem
Existing oxide thin film transistors face challenges in minimizing damage to the oxide semiconductor layer and achieving effective channel control and reduced short channel effects.
Innovation Solution
A semiconductor device design featuring a trench structure with an oxide semiconductor layer formed along the surfaces of source and drain patterns, an upper gate pattern filling the trench, and a stacked structure of insulation and conductive layers to enhance channel control and reduce damage during etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the oxide thin film transistor is formed spaced apart from the substrate surface, then damage to the oxide semiconductor layer is minimized, but channel control ability by the gate electrode deteriorates
Solution Approach 1:
The patent introduces a vertical stacked structure with multiple gate electrodes (lower gate electrode and upper gate electrode) positioned at different heights above the substrate. This three-dimensional gate configuration enables effective channel control while maintaining the oxide semiconductor layer at an elevated position formed after the gate electrodes, thus minimizing damage during fabrication.
Solution Approach 2:
The gate control function is divided into two segments: a lower gate electrode positioned closer to the substrate for basic channel control, and an upper gate electrode positioned higher for enhanced control and compensation. This segmentation allows each gate to optimize its function while the oxide semiconductor layer remains protected at an elevated position.
2Object-affected harmful factors
If the oxide thin film transistor is formed spaced apart from the substrate surface, then damage to the oxide semiconductor layer is minimized, but short channel effect increases
Solution Approach 1:
The vertical stacked gate structure with lower and upper gate electrodes at different heights creates a three-dimensional electric field distribution that extends laterally along the channel. This dimensional approach enhances gate control over the channel region, effectively suppressing short channel effects while allowing the oxide semiconductor layer to be positioned at an elevated, protected level.
Solution Approach 2:
The patent employs a composite gate structure combining lower gate electrode, lower gate insulation layer, and upper gate electrode with upper gate insulation layer. This composite configuration creates a distributed capacitance effect that extends gate control laterally, counteracting short channel effects while maintaining the protective spacing from the substrate surface.
3Device complexity
If a simple gate structure is used, then device complexity is reduced, but channel control ability deteriorates
Solution Approach 1:
The patent transitions from a planar two-dimensional gate structure to a vertical three-dimensional stacked gate structure. By adding the height dimension with lower and upper gate electrodes at different elevations, the design achieves superior channel control capability while maintaining a relatively simple fabrication process and material composition.
Data Source
AI summary
A semiconductor device includes: a first insulation layer disposed on a substrate; a lower gate pattern disposed on the first insulation layer; a second insulation layer covering at least a portion of the lower gate pattern; a first lower gate insulation layer disposed on the lower gate pattern and the second insulation layer; a source pattern and a drain pattern disposed on the first lower gate insulation layer, wherein the source pattern and the drain pattern are spaced apart from each other to include a trench facing the lower gate pattern; an oxide semiconductor layer formed along surfaces of the source and drain patterns and a bottom surface of the trench; an upper gate insulation layer disposed on the oxide semiconductor layer; and an upper gate pattern disposed on the upper gate insulation layer and filling the trench.