Vertical 2-Transistor Memory Cell for Higher Storage Density
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Solution Overview
Problem
Conventional volatile memory devices face challenges in reducing memory cell size to increase storage density due to physical limitations and fabrication constraints, limiting their ability to store information efficiently.
Innovation Solution
The development of a memory device with a 2T memory cell structure, where two transistors are stacked vertically over a semiconductor substrate, allowing for a smaller footprint and efficient storage of information using a floating-gate charge storage structure, enabling both read and write operations with shared access lines to conserve space and simplify operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory cell structures are used to increase storage density, then more memory cells can be packed in a given area, but physical limitations and fabrication constraints prevent further size reduction
Solution Approach 1:
The patent transitions from planar 2D memory cell layout to a vertical 3D stacked configuration. Two transistors are stacked one above the other over a common substrate, utilizing the vertical dimension to reduce the footprint area. This dimensional change allows more memory cells to be packed into a given device area while avoiding the physical limitations that constrain further reduction of individual cell dimensions in conventional planar designs.
Solution Approach 2:
The patent implements a nested structure where one transistor is positioned directly over another, with shared components such as the substrate and interconnect structures. The second transistor is effectively nested within the vertical space above the first transistor, allowing both devices to occupy a smaller horizontal footprint while maintaining functional independence. This nesting approach maximizes space utilization and increases storage density.
2Quantity of substance
If memory cell size is reduced to increase storage density, then more cells fit in a given area, but fabrication constraints make manufacturing difficult
Solution Approach 1:
By moving to vertical stacking, the patent reduces the horizontal dimensions of each memory cell without proportionally increasing fabrication complexity. The vertical configuration allows standard fabrication processes to be adapted to create stacked transistors, avoiding the need for entirely new manufacturing techniques while achieving higher density.
Solution Approach 2:
The patent combines multiple functions into shared structures: both transistors share a common substrate, and access lines are shared between multiple memory cells. This merging reduces the total number of discrete components that need to be fabricated and assembled, simplifying the manufacturing process while increasing the number of functional memory cells per unit area.
3Quantity of substance
If vertical stacking is implemented to reduce footprint, then storage density increases, but device complexity increases
Solution Approach 1:
The nested vertical stacking configuration consolidates multiple transistors into a compact footprint by positioning them one above the other. While the vertical structure adds three-dimensional complexity, it reduces the horizontal spread and allows for shared support structures, interconnects, and substrate regions, which can offset the increased structural complexity through resource sharing.
Solution Approach 2:
The patent implements multi-functionality through shared access lines and common substrate regions that serve multiple stacked transistors. A single access line can control multiple transistors in the stack, and the substrate provides common support and electrical connections for all devices. This universality reduces the total number of separate components needed, balancing the increased vertical structural complexity with reduced horizontal component count.
Data Source
AI summary
Some embodiments include apparatuses and methods of forming the apparatus. One of the apparatuses and methods includes a memory cell having a first transistor and a second transistor located over a substrate. The first transistor includes a channel region. The second transistor includes a channel region located over the channel region of the first transistor and electrically separated from the first channel region. The memory cell includes a memory element located on at least one side of the channel region of the first transistor. The memory element is electrically separated from the channel region of the first transistor, and electrically coupled to the channel of the second transistor.