Multi-Gate IC Layout for FinFET and GAA Leakage Control
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Solution Overview
Problem
The integration of different multi-gate devices, such as FinFETs and GAA transistors, on a single integrated circuit is challenging due to dimensional differences, leading to processing issues like oxidation inconsistencies, which affect performance and leakage current.
Innovation Solution
A semiconductor device layout that combines Nanowire, Nanosheet, and FinFET transistors, with specific layout options and isolation structures, allowing for the integration of these devices on a single substrate, optimizing gate control and reducing leakage while maintaining design flexibility for speed and power optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different multi-gate devices (FinFETs and GAA transistors) are integrated on a single integrated circuit, then device performance and functionality are improved, but manufacturing complexity and processing consistency deteriorate due to dimensional differences
Solution Approach 1:
The integrated circuit is divided into separate first and second regions, where the first region houses FinFET devices and the second region houses GAA transistor devices. This spatial segmentation allows each transistor type to be manufactured and processed independently with optimized parameters, avoiding the conflicts that would arise from trying to process both types together in the same region.
Solution Approach 2:
Different processing conditions and structural parameters are applied to different regions of the integrated circuit. The first region has parameters optimized for FinFET manufacturing while the second region has parameters optimized for GAA transistor manufacturing. This local customization of quality parameters enables both transistor types to achieve their optimal performance without compromising each other.
2Area of stationary object
If different multi-gate devices with different dimensions are processed together, then integration density is improved, but oxidation consistency and manufacturing precision deteriorate
Solution Approach 1:
The circuit is segmented into distinct regions for different transistor types, allowing oxidation and other processing steps to be performed with region-specific parameters. This enables high precision oxidation for each transistor type without the compromises that would result from uniform processing across the entire chip.
Solution Approach 2:
The patent utilizes vertical stacking in the second region for GAA transistors, arranging multiple transistor layers in the vertical dimension. This dimensional approach increases integration density without requiring all devices to have the same planar dimensions, thereby accommodating dimensional variations while maintaining processing precision.
3Area of stationary object
If FinFET and GAA transistor cells are integrated without separation, then area utilization is improved, but gate control and leakage reduction deteriorate
Solution Approach 1:
By separating FinFET and GAA transistor cells into different regions, each cell type can maintain its optimized gate control architecture without interference from the other. The isolation structures prevent cross-contamination of electrical characteristics, ensuring that each transistor type achieves its intended low-leakage performance.
Solution Approach 2:
Isolation structures are introduced as intermediary elements between the first and second regions containing different transistor types. These isolation structures act as mediators that electrically separate the two transistor types while allowing both to coexist on the same substrate, preventing leakage paths between different transistor regions.
Data Source
AI summary
Integrated circuit having an integration layout and the manufacturing method thereof are disclosed herein. An exemplary integrated circuit (IC) comprises a first cell including one or more first type gate-all-around (GAA) transistors located in a first region of the integrated circuit; a second cell including one or more second type GAA transistors located in the first region of the integrated circuit, wherein the second cell is disposed adjacently to the first cell, wherein the first type GAA transistors are one of nanosheet transistors or nanowire transistors and the second type GAA transistors are the other one of nanosheet transistors or nanowire transistors; and a third cell including one or more fin-like field effect transistors (FinFETs) located in a second region of the integrated circuit, wherein the second region is disposed a distance from the first region of the integrated circuit.