3D DRAM Transistor Gate Oxide Rounding for Leakage Reduction
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Solution Overview
Problem
Three-dimensional (3D) DRAMs face challenges with thin semiconductor channels that suffer from strong electric field-enhanced off-state leakage due to gate corners, leading to increased source-to-drain leakage current and reduced retention time, while vertical integration introduces mechanical stress and electrostatic control issues.
Innovation Solution
Implementing local oxidation to create a rounded gate edge profile with increased oxide thickness at the channel ends and rounded corner edges in gate-all-around transistors, reducing the gate-induced electric field and off-state leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If thin semiconductor channels are used in vertically integrated 3D DRAM, then memory density per chip is increased, but off-state leakage current increases due to gate corner electric fields
Solution Approach 1:
The gate oxide thickness is varied locally around the gate structure - thinner oxide at the gate center for better electrostatic control and thicker oxide at the gate corners to reduce electric field concentration. This local variation in oxide thickness addresses the specific problem of corner-induced leakage while maintaining overall channel performance.
Solution Approach 2:
The gate corners are rounded to create a curved gate edge profile instead of sharp corners. This curvature reduces the electric field concentration at corner regions, thereby reducing the gate-induced off-state leakage current while maintaining the vertical integration benefits for high density.
2Object-generated harmful factors
If gate corners are rounded to reduce electric field concentration, then off-state leakage is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The gate oxide thickness parameter is changed as a means to achieve corner rounding effects. By controlling oxide growth conditions and using selective oxidation techniques, the gate oxide thickness is varied to create the desired rounded profile effect, which reduces leakage while providing a manufacturable approach through parameter control rather than direct geometric machining.
3Quantity of substance
If vertical integration is implemented to increase memory density, then chip area is reduced, but mechanical stress and electrostatic control issues arise
Solution Approach 1:
The gate oxide thickness is locally optimized at different positions around the gate structure. Thinner oxide at the gate center maintains good electrostatic control for the channel, while thicker oxide at the corners reduces electric field concentration. This local optimization addresses electrostatic control issues in vertically integrated structures.
Solution Approach 2:
The solution moves from two-dimensional planar gate structures to three-dimensional gate-all-around structures that wrap around the channel. This dimensional change provides better electrostatic control in vertically integrated 3D DRAM by surrounding the channel from multiple directions, while the gate oxide thickness variation adds another layer of control dimension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances DRAM retention time by minimizing off-state band-to-band leakage and improves fabrication methods for 3D DRAM arrays with non-uniform gate-oxide geometries and rounded corner profiles.
Implementation Method 1
a gate oxide surrounding the silicon channel
Implementation Method 2
the gate-induced electric field in the channel-drain and channel-source junctions
Data Source
AI summary
A method may include operations associated with providing a stack of layers, the layers separated by a dielectric between the layers, each layer comprising a plurality of unit cells separated by the dielectric between the plurality of unit cells, each unit cell including a silicon channel, a gate oxide surrounding the silicon channel in at least two dimensions, and a gate metal surrounding the gate oxide in the at least two dimensions, the operations including recess etching to remove a portion of the gate metal in each unit cell and applying an oxide growth process to the gate oxide in each unit cell.