CAD Circuit Design TRIZ Cases

DI-based context curation combines user and circuit contexts to deliver timely, relevant actions without overwhelming network users.

A timing interface maps PTP-synced traffic schedules into the emulator domain for precise IEEE 802.1Qbv compliance testing.

Loop-length iteration speeds formal liveness verification in circuits by finding counterexamples with less time and compute.

Concurrent static noise analysis propagates waveform scenarios across voltage domains to cut runtime and memory while avoiding IC over-fixing.

Adds new NoC wire connections while checking turn cycles during synthesis, preventing runtime deadlocks and preserving data throughput.

Grouping hybrid bumps by pitch enables representative point-to-point simulation, cutting 3DIC verification time and compute load.

Automated rule checking screens test and simulated IC data before parameter extraction, reducing manual effort and improving modeling accuracy.

Parallel external memory accesses are reordered by a generated scheduler circuit to match DDR-class memory behavior and meet target circuit performance.

A cloud-native NoC environment validates linked sub-topologies, handling clock-domain crossing and data-width mismatches in SoC communication.

Automated adapter insertion helps NoC paths cross clock domains and timing regions without deadlock or distance violations.

Pitch-based grouping lets representative hybrid bump simulations cover many 3DIC connections, reducing verification runtime and manual effort.

A configurable FIFO core spans Xilinx and Intel FPGA families, cutting implementation effort while balancing RAM use and timing closure.

Isolation-gate backside contacts route signals below standard cells, easing access limits while cutting resistance, RC delay, and parasitics.

A control circuit monitors channel utilization and temporarily reassigns interconnect wires to relieve bandwidth imbalance and raise throughput.

Time-ordered event propagation traces complex clock paths accurately, cuts manual false-path handling, and helps detect glitches.

Models big vias during global routing by adjusting grid-cell capacity, improving congestion maps and avoiding spacing violations before detailed routing.

Multiple conflict graphs and dynamic programming select standard cell pin access points that avoid rule violations and improve routing estimation.

Different scaling factors for shrinkable and fixed IC regions reduce DRC errors and manual fixes during layout migration.

ML-based 3D package modeling predicts IC packaging costs across architecture scenarios, cutting estimation time and aiding selection.

Monte Carlo timing models capture low-voltage process variation in ICs, improving delay margin accuracy without excessive energy loss.

FPGA-based precision testing identifies workload-specific encoding sizes for ML ASICs, cutting register overhead and compute time while preserving accuracy.

Local oxidation thickens and rounds 3D DRAM gate corners to cut off-state leakage and improve retention time.

Adjusting power-line and signal-line widths within a standard cell cuts resistance and improves speed without increasing cell area.

Formal verification finds ungated idle sequential elements without stimulus signals, enabling clock and data gating to cut IC power use.

Two reinforcement learning models automate macro placement, verification, and IP core resizing to speed chip floorplanning and improve layout quality.

Signals are grouped by update cycles and sampled with separate clocks to capture more internal waveforms without slowing circuit emulation.

Automatically merges board netlists to map MCU pins, detect signal conflicts, and reconfigure peripherals for compatible expansion boards.

Poly cut placement tunes different poly extension lengths to control pMOS and nMOS threshold shifts and improve circuit speed.