Region-Based IC Layout Shrinking for DRC-Safe Migration
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Solution Overview
Problem
The linear shrink approach in IC design layout migration leads to errors and design rule check (DRC) issues due to uniform scaling of all features, particularly affecting non-shrinkable circuits like analog circuits and high-speed integrated circuits.
Innovation Solution
A non-uniform shrinking method is applied, where different scaling factors are used for shrinkable and non-shrinkable regions, adjusting layout patterns to maintain performance and reduce DRC errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If linear shrink approach is used for layout migration, then manufacturing process advancement is achieved, but DRC errors and design rule violations increase
Solution Approach 1:
The patent applies different scaling factors to different regions of the IC layout based on their shrinkability characteristics. Shrinkable regions (combinational logic, memory) use one scaling factor while non-shrinkable regions (analog circuits, high-speed interfaces) use another scaling factor or no scaling, thereby maintaining DRC compliance while achieving overall manufacturing advancement.
2Ease of operation
If uniform scaling is applied to all layout features, then layout migration simplicity is maintained, but performance degradation occurs in non-shrinkable circuits
Solution Approach 1:
The patent identifies and categorizes different circuit regions based on their scaling characteristics. Shrinkable regions are scaled uniformly to simplify the process, while non-shrinkable regions are selectively excluded or scaled differently to preserve their performance, thus balancing ease of operation with circuit reliability.
Solution Approach 2:
The IC layout is segmented into multiple regions based on circuit type and shrinkability. This segmentation allows the migration process to apply different scaling strategies to different segments, maintaining both process simplicity and performance integrity.
3Manufacturing precision
If manual corrections are performed to fix DRC errors, then layout accuracy is improved, but time consumption and effort increase significantly
Solution Approach 1:
The patent performs preliminary identification and classification of shrinkable and non-shrinkable regions before the actual scaling process. This preliminary action allows the system to pre-determine appropriate scaling factors for each region, preventing DRC errors before they occur and eliminating the need for extensive manual corrections.
Solution Approach 2:
The migration system automatically identifies region types, determines scaling factors, and applies scaling without requiring manual intervention. The system serves itself by using built-in rules and algorithms to handle the entire migration process, thereby maintaining layout accuracy while minimizing time consumption.
Data Source
AI summary
A method of making a semiconductor device includes determining a first scaling factor for a first region of a first device layout, wherein the first region comprises a first plurality of conductive patterns. The method further includes determining a second scaling factor for a second region of the first device layout, wherein the second region comprises a second plurality of conductive patterns, and the first device layout comprises an interconnect pattern extending from the first region to the second region. The method further includes generating a second device layout. Generating the second device layout includes adjusting the interconnect pattern based on the first scaling factor and the second scaling factor.