Dynamic Chip Floorplanning With RL-Based Macro Placement
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Solution Overview
Problem
Traditional floorplanning methods for integrated circuits are computationally challenging and time-consuming, often leading to suboptimal macro placements and blockages, especially with large numbers of functional blocks, necessitating a more efficient and automated approach.
Innovation Solution
A dynamic chip floorplanning method utilizing reinforcement learning for macro placement and floorplan optimization, involving a macro placer, verifier, and frame resizer to iteratively adjust placements and resize IP cores until predetermined standards are met, leveraging two reinforcement learning models for efficient design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional floorplanning methods are used, then the process is computationally challenging and time-consuming, but the results are suboptimal macro placements and blockages
Solution Approach 1:
The patent replaces traditional mechanical optimization algorithms with reinforcement learning models that have been trained to generate optimal floorplans. The first reinforcement learning model handles macro placement while the second handles floorplan optimization, substituting complex computational mechanisms with AI-based decision-making systems that achieve both speed and quality improvements
Solution Approach 2:
The system performs self-verification through an automated verification process that checks placement validity and optimality. The reinforcement learning models inherently learn from validation feedback during training, enabling the system to self-correct and improve placement quality without external intervention
2Adaptability or versatility
If more functional blocks are added to the chip design, then the chip functionality is enhanced, but the floorplanning complexity and time increase significantly
Solution Approach 1:
The patent segments the floorplanning process into two distinct stages handled by separate reinforcement learning models: the first model handles macro placement within IP cores while the second model optimizes the overall floorplan layout. This segmentation allows each model to specialize in specific aspects, improving overall efficiency when handling large numbers of functional blocks
Solution Approach 2:
The system performs preliminary macro placement using the first reinforcement learning model before proceeding to floorplan optimization with the second model. This preliminary action establishes a solid foundation that reduces the complexity of subsequent optimization steps, enabling efficient handling of designs with many functional blocks
3Ease of operation
If manual intervention is used in floorplanning, then design control is maintained, but human resource expenditure increases
Solution Approach 1:
The patent implements an automated verification system that independently checks placement validity and optimality without requiring manual review. The reinforcement learning models generate designs that inherently satisfy design constraints, eliminating the need for human verification while maintaining design quality and control
Solution Approach 2:
The system incorporates automated feedback loops where the verification process provides immediate validation of placement decisions. This feedback mechanism ensures design control is maintained through automated means, allowing the system to self-correct and refine placements without human intervention
Data Source
AI summary
A dynamic chip floorplanning method includes a macro placer performing macro placements inside a plurality of intellectual property (IP) cores based on a first reinforcement learning model, a verifier performing criteria verification to check if the macro placements satisfy a predetermined standard, a frame resizer resizing a set of IP cores whose macro placements satisfy the predetermined standard, the set of IP cores being a subset of the plurality of IP cores, and a floorplanner adjusting a floorplan to optimize positions and frames of the plurality of IP cores on chip top based on a second reinforcement learning model when none of the plurality of IP cores is to be further resized.