Formal Clock Gating Analysis for Idle Sequential Elements
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for determining clock gating in integrated circuits rely on simulations with specific stimulus input signals, which may miss scenarios where clock gating is necessary, leading to inefficient power consumption due to active clock signals in idle sequential elements.
Innovation Solution
A formal verification process identifies sequential elements that are not clocked in the circuit design, allowing for the addition of clock gating through a software tool that analyzes the circuit without requiring stimulus input signals, and also identifies opportunities for data gating to further reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If simulation-based methods are used to identify clock gating opportunities, then power consumption can be reduced by gating clocks to idle sequential elements, but the completeness of identification is insufficient because specific input stimulus signals may cause scenarios to be missed
Solution Approach 1:
The patent replaces the simulation-based mechanical approach with a formal verification methodology. Instead of applying specific stimulus signals and observing circuit behavior dynamically, the invention uses static analysis with assertion properties to mathematically prove whether sequential elements are clocked under any possible input conditions. This substitution ensures complete identification of clock gating opportunities without relying on stimulus sufficiency.
2Reliability
If multiple iterations with different input stimuli are performed to improve identification completeness, then more clock gating scenarios can be found, but the complexity and time consumption of the process increases
Solution Approach 1:
The patent changes the fundamental parameter of the verification approach from dynamic simulation with varying stimulus signals to static formal verification with assertion properties. By transforming the problem from observing circuit behavior under multiple stimulus conditions to mathematically proving clocking behavior through logical assertions, the methodology achieves complete identification in a single verification pass rather than requiring multiple iterative simulations.
3Measurement precision
If formal verification with assertion properties is used to identify unclocked sequential elements, then clock gating opportunities can be accurately identified without stimulus signals, but the circuit design must be modified to add clock gating logic
Solution Approach 1:
The patent performs preliminary analysis using formal verification to identify all sequential elements that should be clock-gated before finalizing the circuit design. By using assertion properties to prove which sequential elements are unclocked under any input conditions, the methodology enables designers to add clock gating logic in advance, ensuring power optimization is built into the design rather than added as an afterthought.
Data Source
AI summary
A method includes receiving a circuit design, identifying sequential elements and corresponding clocks in the circuit design, and identifying sequential elements that are not clock gated in the circuit design by running a first formal verification process on the circuit design. The method further includes modifying the circuit design to add clock gating for at least one sequential element that was identified as not being clock gated to generate a first modified circuit design.