Static Noise Analysis Across Multi-Voltage IC Domains

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Solution Overview

Problem

Performing static noise analysis in integrated circuits with multiple voltage domains is time-consuming and memory-intensive, leading to potential over-fixing issues that affect power, performance, and area (PPA) of the IC.

Innovation Solution

A system and method for performing simultaneous multi-scenario static noise analysis across multiple voltage domains by generating a noise and timing graph, levelizing it, performing timing analysis, and propagating noise waveforms to identify and fix violations concurrently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If individual simulations are performed for each subcircuit in the presence of various noise sources, then noise analysis accuracy is improved, but analysis time and memory usage increase significantly

Engineering Contradiction:
Improvenoise analysis accuracyVSAvoidanalysis time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The circuit design is divided into multiple subcircuits that are analyzed separately. Each subcircuit is broken down into smaller components, and noise analysis is performed on individual subcircuits rather than the entire design, reducing the computational burden while maintaining accuracy through systematic propagation of noise effects through the segmented structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The subcircuits are sorted and organized in advance using a levelization technique similar to static timing analysis. This preliminary sorting establishes a analysis order where all preceding circuits that could affect a node's inputs are analyzed before the node itself, allowing for efficient sequential processing without requiring repeated full-circuit simulations.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If comprehensive noise analysis is performed across multiple voltage domains, then noise violation detection capability is improved, but computational resources required increase

Engineering Contradiction:
Improvenoise violation detection capabilityVSAvoidcomputational resources
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The noise analysis methodology is designed to handle multiple voltage domains simultaneously using a unified approach. The same analysis techniques and algorithms are applied across different voltage domains, allowing the system to detect noise violations in all domains through a single comprehensive process rather than requiring separate specialized analyses for each domain.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

Multiple voltage domains are analyzed together in a consolidated manner. The noise propagation analysis merges the analysis of different voltage domains by propagating noise effects through the interconnected subcircuits across domain boundaries, allowing simultaneous detection of violations in all domains while sharing computational resources efficiently.

Inventive Principle:
Principle #5Merging (Combining)

3Loss of information

If static noise analysis is extended to include sensitivity analysis, then circuit response characterization is improved, but analysis complexity increases

Engineering Contradiction:
Improvecircuit response characterizationVSAvoidanalysis complexity
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

The sensitivity analysis is integrated continuously with the noise propagation analysis rather than being performed as a separate subsequent step. As noise effects are propagated through each subcircuit, sensitivity information is simultaneously calculated and accumulated, providing continuous characterization of circuit response to input noise without requiring additional discrete analysis passes.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS12518077B1Simultaneous multi-scenario static noise analysis
Publication Date: 2026.01.06 SYNOPSYS INC
  • US12518077B1 patent drawing
  • US12518077B1 patent drawing
  • US12518077B1 patent drawing

AI summary

A computer-implemented method for performing static noise analysis in an electronic design of an integrated circuit includes accessing, by a processing device, the electronic design including a plurality of voltage domains, wherein each voltage domain includes one or more functional elements and one or more domain voltages. The method further includes performing a timing analysis of the electronic design and determining respective signal arrival timing windows for the one or more functional elements in the electronic design. The method further includes generating a noise waveform at a first functional element based on the signal arrival timing windows and slews of aggressor nets of a first functional element in a first voltage domain of the plurality of voltage domains. The method further includes determining a number of noise waveforms reaching a second functional element in a second voltage domain based on the plurality of voltage domains and the one or more domain voltages in the plurality of voltage domains, and propagating at least one noise waveform of the number of noise waveforms to the second functional element.