Big Via Modeling in Global Routing for DRC Spacing Compliance
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Solution Overview
Problem
Conventional global routing processes in electronic design automation (EDA) fail to address minimum spacing violations caused by big vias, which worsen as technology nodes shrink, due to lack of knowledge about track assignments and pitch differences between layers.
Innovation Solution
Detect and model big vias during global routing by reducing routing capacity of grid cells based on via demands and capacities, generating a more accurate congestion map to mitigate spacing violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional global routing processes are used, then routing speed is maintained, but minimum spacing violations occur due to lack of via knowledge
Solution Approach 1:
The patent detects and models vias during global routing before detailed routing begins. By identifying via locations, enclosure requirements, and pitch differences in advance, the system prepares congestion maps that account for future spacing constraints, preventing DRC violations before they occur in the detailed routing phase.
Solution Approach 2:
The patent extends traditional 2D grid-based routing to 3D by incorporating via information across multiple layers. It models via enclosures and pitch differences that span different metal layers, adding a vertical dimension to congestion analysis and enabling the system to predict spacing violations that affect multiple layers simultaneously.
2Reliability
If big via issues are addressed during global routing, then spacing violations are prevented, but computational complexity increases
Solution Approach 1:
The patent applies via modeling selectively to regions where big vias are detected rather than uniformly across the entire design. By identifying specific areas with pitch differences and enclosure requirements, the system concentrates computational resources on problematic regions, reducing overall computational power requirements while maintaining spacing violation prevention.
Solution Approach 2:
The patent dynamically adjusts routing capacity parameters in grid cells based on via demands and enclosure requirements. By modifying capacity values locally around via locations and adjusting them according to detected pitch differences, the system efficiently incorporates via constraints without requiring complete re-computation of the entire routing problem.
3Measurement precision
If via modeling is performed during global routing, then congestion map accuracy improves, but routing time increases
Solution Approach 1:
The patent implements partial via modeling by focusing computational effort on detecting and modeling only the most critical vias that cause spacing violations, rather than equally processing all vias. By identifying via enclosures with pitch differences and applying modeling selectively, the system achieves sufficient congestion map accuracy without the full computational overhead of complete via analysis.
Data Source
AI summary
Various embodiments provide for detecting and modeling vias of a circuit design during global routing, which may be part of electronic design automation (EDA). In particular, various embodiments described herein detect and model a big via during a global routing process, which can help mitigate or avoid minimum spacing violations by big vias.