Cloud-Native NoC Sub-Topology Validation Across Clock Domains
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Solution Overview
Problem
The integration of complex microprocessor systems in SoCs faces challenges such as long wire lengths, signal propagation delays, data synchronization issues, and bandwidth limitations due to direct bus wiring, which are exacerbated by increasing chip sizes and added functions, necessitating improved communication methods.
Innovation Solution
A collaborative Network-on-Chip (NoC) development environment (CNDE) based on cloud-native software enables graphical design and validation of NoC topologies, allowing for the creation and interfacing of sub-topologies with different clock frequencies, and includes an interfacing block to ensure proper communication between sub-topologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If direct bus wiring is used for subsystem communication, then integration is simple, but wire lengths become long causing signal propagation delays
Solution Approach 1:
The patent divides the communication network into multiple NoC sub-topologies, each handling local communication within a region. This segmentation reduces the maximum communication distance within each sub-topology, thereby reducing signal propagation delays while maintaining modular integration simplicity.
Solution Approach 2:
The patent introduces NoC routers as intermediary nodes between subsystems. These routers manage packet routing and forwarding, enabling communication between distant subsystems without requiring direct long wire connections, thus reducing signal propagation delays while maintaining integration simplicity.
2Adaptability or versatility
If chip size increases to add more functions, then functionality improves, but wire lengths and propagation delays increase
Solution Approach 1:
The patent organizes the large chip into multiple NoC sub-topologies, each managing a specific region or function. This segmentation allows the chip to scale in functionality by adding more sub-topologies without proportionally increasing communication distances, as local communications are handled within each sub-topology.
Solution Approach 2:
The patent employs a mesh-like NoC topology that adds spatial dimensions to the communication architecture. Instead of linear bus extensions, data can route through multiple dimensions (horizontal and vertical paths), providing alternative shorter paths and reducing propagation delays in large chips.
3Productivity
If different clock frequencies are used in subsystems, then performance optimization is possible, but data synchronization becomes problematic
Solution Approach 1:
The patent introduces clock domain crossing (CDC) interfaces as intermediary components at the boundaries of NoC sub-topologies. These CDC interfaces handle clock frequency translation and synchronization, allowing subsystems to operate at different optimized frequencies while maintaining reliable data synchronization across clock domains.
4Adaptability or versatility
If manual design and validation is performed, then flexibility is high, but time consumption and human intervention increase
Solution Approach 1:
The patent implements automated design and validation tools that enable the NoC architecture to self-verify its correctness. The system automatically checks for routing correctness, connectivity, and potential design errors, reducing the need for manual validation while preserving design flexibility through configurable parameters and modular structures.
Data Source
AI summary
A collaborative Network-on-Chip (NoC) development environment (CNDE) is accessed. The CNDE is based on cloud-native software. The CNDE enables graphical design of a NoC topology within a database. A first NoC sub-topology within the NoC topology is created within the CNDE. The creating includes coupling a first network initiator, a first router, and a first network target. A second NoC sub-topology within the NoC topology is generated within the CNDE. The generating includes coupling a second network initiator, a second router, and a second network target. An interfacing block is inserted within the CNDE, enabling two-way communication between the first NoC sub-topology and the second NoC sub-topology. The NoC topology is validated. The validating ensures that the first network initiator is coupled to the first and second network targets, and that the second network initiator is coupled to the first and second network targets.