Backside Contact Layout for Low-Resistance Standard Cell Routing
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Solution Overview
Problem
As standard cells in semiconductor devices become smaller, providing access and reducing trace resistances within the cells becomes challenging, affecting performance and increasing costs due to parasitic issues and process complexity.
Innovation Solution
Utilizing backside metal layers for signal routing through isolation gates, which provide low-resistance connections between active gates and backside metal layers, reducing RC delay and improving area utilization without significant process changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If standard cell size is reduced to increase circuit density, then area utilization improves, but access to components and signal routing becomes more difficult
Solution Approach 1:
The patent introduces backside metal layers (MB1, MB2) beneath the standard cell to provide additional routing dimensions. Signals can be routed through these subsurface layers, effectively adding a vertical dimension to the routing space and eliminating the need to increase cell area for routing purposes.
Solution Approach 2:
The patent segments the routing function between topside metal layers (for power and some signals) and backside metal layers (for signal routing). This segmentation allows standard cells to maintain small area while accessing components through multiple independent routing paths.
2Area of moving object
If standard cell size is reduced to increase circuit density, then area utilization improves, but trace resistances increase affecting performance
Solution Approach 1:
By routing signals through backside metal layers that extend beneath the standard cell, the patent creates longer, lower-resistance signal paths. These subsurface traces can span multiple cells without requiring larger individual cell areas, thus maintaining density while reducing resistance.
Solution Approach 2:
The backside metal layers serve multiple functions: they provide signal routing, reduce parasitic resistance, and enable connections across multiple standard cells. This multi-functionality allows a single routing infrastructure to address both density and performance requirements.
3Device complexity
If traditional topside routing is used, then process complexity remains low, but parasitic issues increase affecting performance
Solution Approach 1:
The patent uses isolation gates and their associated metal fills as intermediary structures to connect topside and backside routing. These intermediaries provide low-resistance contact points between surface and subsurface layers, reducing parasitic effects without requiring complex through-silicon vias or deep etching processes.
Solution Approach 2:
The isolation gate structures, which are already present for device isolation purposes, are repurposed to provide signal routing functionality. This self-service approach eliminates the need for additional dedicated routing structures, maintaining process simplicity while reducing parasitics through the added backside routing capability.
Data Source
AI summary
A cell layout that may be implemented in FinFET devices or other FET devices is disclosed. The cell layout utilizes an isolation gate structure to provide routing between a signal input of an active gate and a backside metal layer. The isolation gate structure includes a metal fill surrounded by gate spacers. The metal fill connects between the topside layers in the device and the backside layer in the device. The metal fill may be connected to the signal input of the active gate through routing either in a topside metal layer or a metal wire placed in a topside insulating layer. The isolation gate structure can be part of any standard cell being placed at a cell boundary or inside the cell to provide access to backside signal routing. Additionally, filler cells with isolation gate structures may provide backside routing connections for adjacent functional cells.