Formal Circuit Liveness Checking With Loop-Length Counterexamples

The patent segments the verification process by dividing the state space exploration into different loop length iterations. Instead of attempting to verify all possible loop lengths simultaneously, the system divides the verification into discrete iterations where each iteration checks for counter-examples with a specific loop length, progressively increasing the length in subsequent iterations. This segmentation makes the otherwise intractable problem manageable and enables parallel processing of different loop length ranges.

The patent applies preliminary action by first checking for counter-examples with smaller loop lengths before proceeding to larger loop lengths. The system performs preliminary verification with constrained loop length ranges, and only when no counter-examples are found does it proceed to expand the search to larger loop lengths. This preliminary checking approach allows the system to quickly identify obvious bugs while preparing for more comprehensive verification if needed.

The patent implements self-service by enabling the formal verification system to automatically explore the state space and find counter-examples without requiring manual intervention. The system autonomously performs loop length iteration, state space exploration, and counter-example identification. The automated process maintains verification precision by systematically checking liveness properties while significantly improving productivity through computer-based exhaustive search capabilities.

The patent applies parameter changes by dynamically adjusting the loop length parameter during verification. The system changes the loop length parameter across different iterations, starting from smaller values and progressively increasing to larger values. This parameter variation enables the system to efficiently search the state space while maintaining the ability to find counter-examples of different complexities, thereby balancing precision and productivity.

The patent applies dynamics by making the loop length parameter dynamic rather than fixed. The system adaptively adjusts the loop length across different iterations, starting with smaller lengths and progressively increasing to larger lengths. This dynamic approach allows the verification process to balance completeness and resource consumption by exploring the state space in a structured, progressive manner rather than attempting exhaustive search at maximum depth from the outset.

The patent implements periodic action through iterative verification cycles with different loop length ranges. The system performs verification in periodic iterations, where each iteration focuses on a specific loop length range. This periodic structure allows the system to systematically cover the entire state space while consuming computational resources in manageable increments, improving bug detection completeness without overwhelming resource requirements.