NoC Topology Modification for Deadlock-Free Wire Routing
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Solution Overview
Problem
Network-on-chip (NoC) topologies can experience deadlocks during runtime, leading to stalled states, which are difficult to resolve without resetting the system, and existing methods for modifying NoC topologies to avoid deadlocks are inefficient.
Innovation Solution
A computer-implemented method and ECAD tool that analyze existing NoC topologies, add new wire connections, and ensure no cycles are formed by turns, using machine learning models to identify and break potential deadlocks during synthesis, thereby creating a deadlock-free topology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If new wire connections are added to modify NoC topology, then connectivity and data throughput are improved, but cycles may be created causing deadlocks
Solution Approach 1:
The patent applies preliminary action by detecting potential cycles that could cause deadlocks during the topology modification process, before they can affect runtime operation. The system identifies cycles in the graph representation of the NoC topology and breaks them by removing edges (wire connections) proactively during design, preventing deadlocks before they can occur during chip operation.
Solution Approach 2:
The patent applies the taking out principle by extracting and removing specific wire connections (edges) from the NoC topology that would create cycles. The system identifies problematic connections that form cycles and selectively removes them, maintaining necessary connectivity while eliminating deadlock-causing pathways from the network.
2Productivity
If NoC topology is modified to improve performance, then data throughput increases, but system complexity increases
Solution Approach 1:
The patent applies mechanics substitution by replacing manual, iterative topology modification approaches with an automated algorithmic system. The ECAD tool automatically detects cycles in the NoC topology graph and identifies edges to remove, eliminating the need for manual trial-and-error modifications and reducing design complexity while maintaining performance optimization.
3Reliability
If deadlock detection is performed during runtime, then deadlocks can be identified, but system operation is disrupted requiring resets
Solution Approach 1:
The patent applies preliminary action by performing deadlock prevention during the design phase rather than detection during runtime. The system analyzes the NoC topology beforehand, identifies potential cycle formations, and removes problematic connections before the chip is manufactured and deployed, ensuring deadlock-free operation without runtime intervention or system resets.
Data Source
AI summary
Designing a network-on-chip (NoC) includes accessing an existing NoC topology having existing NoC elements, blockages and existing wire connections. The existing NoC elements include network interface units and switches. The designing further includes creating an updated NoC topology from the existing NoC topology, including adding at least one new wire connection to the existing wire connections. The designing further includes identifying turns and segments in the existing and new wire connections in the updated NoC topology; and ensuring that no cycles are created by the segments that form turns. The updated NoC topology is deadlock-free.