External Memory Access Scheduling for Shared HLS Circuit Generation

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Solution Overview

Problem

Existing high-level synthesis tools generate redundant memory access circuits for multiple modules without considering the performance characteristics of external memories like DDR-SDRAM, leading to inefficient memory usage and suboptimal performance.

Innovation Solution

A circuit design assistance device that automatically generates a scheduler circuit based on external memory specifications and performance, identifying parallel memory accesses and determining an issue order to meet required circuit performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a memory access circuit is generated for each module when multiple modules access memory, then each module can independently access memory, but redundant circuits are generated and memory usage efficiency decreases

Engineering Contradiction:

ImproveIndependent memory access capabilityVSAvoidCircuit redundancy

Core Design Contradiction:

Ease of operationVSDevice complexity

Solution Approach 1:

The patent merges multiple independent memory access circuits into a single shared memory access circuit that serves multiple modules. This eliminates redundant circuits while maintaining the ability of each module to access memory independently through the shared circuit with arbitration control.

Inventive Principle:

Principle #5Merging (Combining)

2Ease of manufacture

If memory access circuits are generated without considering external memory performance characteristics, then circuit generation is simplified, but memory usage efficiency decreases and desired performance cannot be achieved

Engineering Contradiction:

ImproveCircuit generation simplicityVSAvoidMemory usage efficiency

Core Design Contradiction:

Ease of manufactureVSProductivity

Solution Approach 1:

The patent changes the approach from generic circuit generation to parameterized circuit generation that incorporates external memory performance characteristics such as transaction size, access latency, and bandwidth. The scheduler circuit is configured with specific parameters matching the external memory's performance profile to optimize memory usage efficiency.

Inventive Principle:

Principle #35Parameter changes

3Device complexity

If parallel memory accesses are not scheduled optimally, then implementation is simpler, but circuit performance does not meet required performance

Engineering Contradiction:

ImproveScheduling implementation complexityVSAvoidCircuit performance

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent introduces a scheduler circuit as an intermediary component between multiple memory access requests and the shared memory access circuit. This scheduler arbitrates and orders parallel memory accesses optimally based on external memory performance characteristics, achieving required circuit performance without excessive implementation complexity.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20250390652A1Circuit design assistance device, circuit design assistance method, and computer readable medium

Publication Date: 2025.12.25 MITSUBISHI ELECTRIC CORP

AI summary

A scheduling unit (110) of a circuit design assistance device (100) acquires a high-level description (61) including a plurality of external memory accesses from a plurality of modules, required circuit performance (63), and external memory information (64). The scheduling unit (110) identifies external memory accesses that operate in parallel in a circuit, and determines an issue order (72) of the external memory accesses that operate in parallel so as to satisfy the required circuit performance (63). A circuit generation unit (120) of the circuit design assistance device (100) generates a circuit description (65) of an external memory access circuit including a scheduler circuit that issues the external memory accesses that operate in parallel in the issue order (72).