Cell Layout With Poly Cut Positioning for Threshold Voltage Control

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Solution Overview

Problem

The miniaturization of integrated circuits leads to challenges in design and manufacturing, particularly due to variations in poly extension effects affecting transistor threshold voltages, which impact circuit performance.

Innovation Solution

Systematic analysis and positioning of poly cut patterns in the layout design to optimize the poly extension effect, improving the performance of semiconductor cell structures by adjusting the edge-to-edge distances between poly cut patterns and active zone patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If poly extension effect is not optimized, then manufacturing process is simpler, but transistor threshold voltage variations affect circuit performance

Engineering Contradiction:
Improvecircuit performanceVSAvoidlayout design complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by positioning poly cut patterns at specific locations within the cell structure to locally adjust poly extension lengths. Different regions of the cell structure have different poly extension requirements, so poly cuts are strategically placed to provide localized threshold voltage control rather than uniform treatment across the entire structure.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the parameter of poly extension length by introducing poly cut patterns that extend into the gate region. This modifies the effective poly extension length in specific regions, thereby controlling transistor threshold voltages and improving circuit performance while maintaining manufacturing feasibility.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If poly cut patterns are positioned to optimize poly extension effect, then transistor threshold voltage control improves, but manufacturing precision requirements increase

Engineering Contradiction:
Improveedge-to-edge distance controlVSAvoidpoly cut pattern positioning
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent applies preliminary action by pre-calculating and pre-positioning poly cut patterns during the layout design phase. The poly cut patterns are designed with specific edge-to-edge distances from active zone patterns before fabrication, allowing the manufacturing process to follow a predetermined plan rather than requiring real-time adjustments.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The poly cut patterns serve as intermediary structures between the gate region and active zone patterns. These intermediary poly cuts mediate the interaction between different regions by providing controlled extension lengths that balance threshold voltage control with manufacturing feasibility.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If different poly extension lengths are implemented in cell structures, then circuit performance optimizes, but design and manufacturing specifications become stricter

Engineering Contradiction:
Improvecircuit speedVSAvoiddesign specification compliance
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies segmentation by dividing the cell structure into distinct regions with different poly extension characteristics. By segmenting the cell structure and introducing poly cut patterns at specific locations, the design achieves different poly extension lengths in different regions, enabling performance optimization while maintaining compliance with overall design specifications.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250366212A1Cell structure having different poly extension lengths
Publication Date: 2025.11.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250366212A1 patent drawing
  • US20250366212A1 patent drawing
  • US20250366212A1 patent drawing

AI summary

A method includes depositing a gate-strip intersecting two first-type active zones and two second-type active zones correspondingly at channel regions of two first-type transistors and two second-type transistors. The two second-type active zones are between the two first-type active zones. The method also includes determining a difference between poly extension effects of a p-type transistor and poly extension effects of an n-type transistor, and patterning one or more poly cuts intersecting the gate-strip based on the difference.