NoC Path Adapter Insertion Across Clock and Distance Boundaries
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Solution Overview
Problem
Current methods for designing network-on-chip (NoC) topologies in systems-on-chips (SoCs) are time-consuming and inefficient, particularly in handling deadlock-free operations with minimal power and area overhead, and fail to consider intermediate regions during link insertion, leading to potential distance violations and clock domain boundary crossing issues.
Innovation Solution
An electronic computer-aided design (ECAD) tool that generates NoC topologies using a set of constraints and inputs, supports regular network topologies, and inserts adapters to prevent clock domain boundary crossing and distance violations, while allowing incremental synthesis of new connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If manual NoC topology design is performed, then design flexibility and customization are improved, but design time and productivity deteriorate
Solution Approach 1:
The system enables automatic NoC topology generation where the design tool autonomously synthesizes deadlock-free topologies based on input constraints without requiring manual intervention. The tool self-adjusts parameters, selects routing algorithms, and optimizes the topology structure automatically, transforming a manual service into an automated self-service process that maintains flexibility while dramatically improving productivity
Solution Approach 2:
The system utilizes parameter-based constraint input (such as throughput requirements, latency constraints, power limits, and area budgets) to dynamically generate different topology configurations. By changing input parameters, the system automatically produces optimized topologies tailored to specific design requirements, maintaining adaptability while eliminating time-consuming manual design iterations
2Area of stationary object
If intermediate regions are ignored during link insertion, then area utilization is improved, but distance violations and clock domain boundary crossings occur
Solution Approach 1:
The system performs preliminary identification and analysis of intermediate regions before link insertion. The design tool预先 determines which regions lie along potential link paths and evaluates their characteristics (such as clock domain information and distance metrics) in advance, allowing for proactive prevention of distance violations and clock domain boundary crossings while still optimizing area utilization
Solution Approach 2:
The system introduces intermediate regions as mediators in the link insertion process. Rather than ignoring them or treating them as obstacles, the tool uses intermediate regions as evaluation points to determine optimal link routing, ensuring that links are placed to satisfy distance constraints and avoid clock domain boundaries while achieving good area utilization through intelligent path selection
3Device complexity
If deadlock avoidance is managed separately from topology synthesis, then topology optimization is improved, but overall design integration and productivity deteriorate
Solution Approach 1:
The system merges deadlock avoidance mechanisms directly into the topology synthesis process. Rather than treating them as separate sequential steps, the tool integrates deadlock detection, deadlock-free routing algorithm selection, and topology generation into a unified simultaneous optimization process. This produces deadlock-free topologies with optimized performance characteristics while improving overall design integration and productivity
Data Source
AI summary
A design tool is disclosed for generation and synthesis of the network, such as a network-on-chip (NoC). The design tool starts with a deadlock free network design and makes changes or transforms the design to generate a desired NoC, including addressing paths that cross clock domain boundaries or have timing violations. The design tool considers intermediate and proximal regions during the insertion process of distance links, which eliminates distance violations resulting from clock and timing domain traversal by a path.