3D DRAM Memory Structure With Sacrificial Gate-Channel Formation
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to simplify the process and improve the yield of dynamic random access memory (DRAM) as the size of memory devices shrinks, leading to increased manufacturing difficulty and internal stress, which affects response speed, power consumption, and storage density.
Innovation Solution
A method involving the formation of a stacked layer on a substrate with interlayer isolation layers and a sacrificial layer group, including a first, second, and third sacrificial layer, where the second sacrificial layer is removed to form gaps, and a gate and channel layer are formed wrapping the gate layer, reducing internal stress and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of memory continues to shrink to achieve higher storage density, then storage density is improved, but the difficulty of manufacturing process and internal stress increase, leading to reduced yield
Solution Approach 1:
The patent divides the memory structure into multiple stacked layers (first stacked layer, second stacked layer, third stacked layer) with each layer containing multiple memory cells. This segmentation allows the memory to achieve high storage density through vertical stacking while maintaining manageable manufacturing complexity for each individual layer, thereby improving yield despite continuous scaling.
Solution Approach 2:
The patent transitions from planar memory architecture to three-dimensional stacked architecture. By arranging memory cells in multiple layers stacked vertically (adding the vertical dimension), the patent achieves higher storage density without proportionally increasing manufacturing difficulty, as each layer can be fabricated using similar processes scaled to appropriate dimensions.
2Quantity of substance
If the size of memory continues to shrink to achieve higher storage density, then storage density is improved, but internal stress increases, leading to reduced yield
Solution Approach 1:
The patent segments the stressed structure into multiple thin stacked layers rather than creating one large continuous structure. Each layer experiences reduced internal stress due to its smaller dimensions, and the stacking arrangement distributes mechanical stress across multiple interfaces, preventing stress accumulation that would occur in a monolithic shrunk structure.
Solution Approach 2:
By moving to three-dimensional stacking, the patent redistributes internal stress across the vertical dimension. The stress that would concentrate in a two-dimensional shrunk planar structure is dispersed across multiple layer interfaces in the third dimension, reducing the magnitude of internal stress at any single location and improving manufacturing yield.
3Quantity of substance
If conventional manufacturing processes are used for shrunk memory, then manufacturing process complexity increases, but storage density is improved through scaling
Solution Approach 1:
The patent segments the manufacturing process into modular steps for forming each stacked layer independently. Each layer can be fabricated using standardized processes that are then repeated and stacked, avoiding the need for entirely new complex manufacturing techniques. This modular approach maintains process simplicity while achieving high density through vertical integration.
Solution Approach 2:
The patent resolves manufacturing complexity by transitioning to three-dimensional stacking, which allows conventional planar fabrication processes to be applied repeatedly in the vertical dimension. Rather than requiring new complex processes to achieve density in a shrunk planar format, the same processes are stacked vertically, simplifying the overall manufacturing approach while achieving higher storage density.
Data Source
AI summary
The present disclosure relates to a memory and a forming method thereof. The method of forming a memory includes: forming a stacked layer on a surface of a substrate, the stacked layer including interlayer isolation layers arranged at intervals in a first direction and a sacrificial layer group located between adjacent two of the interlayer isolation layers, the sacrificial layer group including a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer sequentially stacked in the first direction, and the stacked layer including a transistor region, where the first direction is a direction perpendicular to a top surface of the substrate; removing the second sacrificial layer in the transistor region to form a first gap; and forming a gate layer and a channel layer wrapping the gate layer in the first gap.