3D DRAM Structure with Segmented Conductive Pillars
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing costs while maintaining the density and efficiency of three-dimensional (3D) DRAM structures, as conventional methods for stacking two-dimensional (2D) structures are costly and inefficient.
Innovation Solution
A semiconductor structure comprising a stack of alternately disposed conductive and dielectric layers with specific conductive pillars and layers formed along the edges and sidewalls, allowing for the creation of 3D DRAM devices with reduced costs through a bit cost scalable process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional methods for stacking two-dimensional (2D) structures are used to create 3D DRAM structures, then the density and volume reduction goals are achieved, but the manufacturing cost increases
Solution Approach 1:
The device defining region is divided into a first portion and a second portion separated from each other. The first conductive pillar is formed in the first portion, while the second and third conductive pillars are formed in the second portion. This segmentation allows different manufacturing approaches for different regions, enabling cost reduction while maintaining density.
Solution Approach 2:
The same manufacturing processes are used to form all DRAM cells in the structure, making the process universal and scalable. This bit cost scalable process eliminates the need for different manufacturing steps for different cell types, thereby reducing manufacturing cost while achieving high density 3D structure.
2Area of moving object
If more electronic devices are stacked layer by layer to increase density, then the footprint is reduced, but the manufacturing complexity and cost increase
Solution Approach 1:
Multiple conductive layers (second conductive layer, third conductive layer) and conductive pillars are integrated within the same device defining region. The stack structure with alternating conductive and dielectric layers combines multiple functional elements vertically, reducing footprint while using unified manufacturing processes to avoid increased complexity.
Solution Approach 2:
The patent transitions from two-dimensional planar structures to three-dimensional vertical stacking. The stack comprises multiple conductive and dielectric layers arranged vertically, with conductive pillars extending through the stack, achieving high density in the vertical dimension rather than expanding horizontally, thus reducing footprint without proportionally increasing manufacturing complexity.
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure has a device defining region. The device defining region includes a first portion and a second portion separated from each other. The semiconductor structure includes a stack. The stack includes first conductive layers and first dielectric layers disposed alternately. The stack has an opening through the stack in the device defining region. The semiconductor structure further includes a second conductive layer, a first conductive pillar, a third conductive layer, a second conductive pillar, and a third conductive pillar. The second conductive layer is disposed along a sidewall of the opening. The first conductive pillar is disposed in the opening in the first portion. The third conductive layer is disposed in the opening along an edge of the second portion. The second conductive pillar and the third conductive pillar are disposed in the second portion and separated from each other.