Digital Storage TRIZ Cases

Segmented conductive pillars in a stacked structure reduce manufacturing costs for high-density 3D DRAM devices.

Junction leakage generates temperature-dependent bias voltages in a sense amplifier, adjusting transistor thresholds to improve read speed at cold temperatures.

A dual operation decoding signal circuit multiplexes read and write signals within a single clock cycle.

A half Heusler alloy-topological semimetal spin injection source generates high-efficiency spin currents via the spin Hall effect.

Storing parity data in additional wordlines enables chip-internal error detection, eliminating off-chip transmission latency and bandwidth usage.

Sensing circuitry performs logical operations and shift decisions directly within the memory array to enable local data processing.

A pre-computation based ternary content addressable memory uses a secondary storage layer to filter match lines before search operations.

A dual port SRAM cell performs XOR and XNOR logic functions through specific read and write port operations.

Resistive memory synapses apply programmable time delays to input signals for precise spike alignment.

A single-ended sense amplifier circuit reduces capacitance at the sense node to improve operating margin during low voltage operations.

A data strobe masking gating signal modifier applies variable time delays to center expected data receipt durations.

A volatile memory analysis system acquires refresh data and displays rates against thresholds on a graphical interface.

Relocating redundant data into defective column latches improves input output rates by removing complex remapping logic.

Back-gate control in SRAM cells improves write ability and read stability while reducing leakage current and power overhead.

Access control circuitry toggles memory arrays between single and dual port modes, minimizing charge interference that causes write failures at high speeds.

Tracking transistors in the word-line under-drive scheme dynamically adjust enable voltage to mitigate read disturb and enhance stability.

Spare logic elements incorporate a cutoff structure that disconnects the source voltage supply, eliminating leakage current paths in idle circuits.

A DRAM integrated circuit monitors row addresses using a two-stage filtering system to identify frequently accessed rows for targeted refresh operations.

Merging write circuits into a single unit halves control signal frequency, reducing central region circuit size while maintaining data access capability.

Constant current drivers drive parallel test currents through resistive memory cells, reducing testing time and cost for high-density arrays.

A reference column uses resistive memory cells to form current paths for precise reference current generation.

Search line driver precharges search lines to intermediate voltage for high accuracy data search.

A hub device architecture shares one external memory among multiple chips to load firmware sequentially.

Dynamic on-die termination adjusts impedance states to manage signal reflections, preventing transmitter attenuation in electrically close memory dies.

Shifted memory cells and shared bit lines maintain uniform layout density, reducing MTJ size irregularity and signal variation.

A memory controller inputs compensation current to lower phase change material resistance in storage cells.

Segmenting equalization into TFFE and VFFE stages reduces ISI jitter without degrading signal integrity or increasing power consumption.

A shared redundancy page buffer array manages data transfer between main and redundant memory arrays to repair defective columns without discarding the device.

A semiconductor device uses a fence structure with pillar portions to stabilize electrical connections between bit line and word line structures.

Dynamic word line voltage adjustment resolves the speed-retention trade-off, simplifying memory hierarchies by allowing DRAM to replace multiple memory types.

A memory management system adjusts programming pulse widths based on stored bit error rate relationships to optimize write operations.

Configurable drive circuitry provides signal pulses to resistance change memory cells for dynamic operational mode selection.

Power management integrated circuit adjusts memory voltage to match host levels.

A strap cell segments bit lines between memory sub-banks, reducing wire loading and data transmission delay without external logic circuits.

Dynamic reference voltage control enables a single input buffer to process DDR4 and LPDDR4 signals accurately without separate dedicated circuits.

Grouped bit line testing with persistent masking latches reduces detection time while preventing leakage currents from short circuits.

A semiconductor path selector routes data strobe signals through multiple input paths during test operations to minimize required test pins.

A sense amplification circuit stabilizes bit line voltages using synchronized PMOS and NMOS transistor control signals.

A resistive memory cell uses two transistors and two resistors to stabilize impedance states for accurate data reading.

Area-aware read assist circuitry recovers degraded read and write margins without incurring timing or power penalties.

A memory cell uses vertically stacked transistors to eliminate separate capacitors.

A reference resistance circuit adjusts its resistance value based on control signals to enable accurate data state differentiation in resistive memory devices.

Interleaved disabled rows protect active data from row disturb attacks while distinct refresh protocols lower power consumption.

A wordline tracking circuit uses a pre-charge mechanism to accelerate bitline recovery.

A resistance change memory sensing method applies threshold and resistance voltages to measure cell currents for data retrieval.

Adaptive source-line voltage boosting reduces sub-threshold leakage without negative supply rails, cutting dynamic power consumption by 20-40%.