Neural Network Circuit with Resistive Memory Delay Lines
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Solution Overview
Problem
Current artificial neural networks lack the ability to effectively consider spike arrival times while maintaining low complexity and chip area, which is essential for efficient signal integration and coincidence detection.
Innovation Solution
A neural network circuit utilizing resistive memory elements to introduce time delays and weights, allowing for the consideration of spike arrival times through synapse circuits with programmable resistive memory elements and capacitors, enabling efficient coincidence detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional artificial neural networks are used, then chip area and complexity are reduced, but the ability to consider spike arrival times is lost
Solution Approach 1:
The patent replaces complex digital timing circuits with passive RC (resistor-capacitor) delay lines. The RC circuits naturally introduce time delays proportional to their time constants, eliminating the need for complex digital logic to track and process spike arrival times. This analog approach to time processing significantly reduces circuit complexity while maintaining the ability to consider spike timing information.
Solution Approach 2:
The patent varies the time delay parameters of different synapse circuits by adjusting RC time constants. Each synapse circuit has a specific delay value that allows it to align spikes from different input channels at specific time offsets. This parameter variation enables the network to process temporal patterns without requiring complex control logic, thus improving adaptability while keeping device complexity low.
2Adaptability or versatility
If RC delay lines are used in synapse circuits, then spike arrival times are considered, but chip area increases
Solution Approach 1:
The patent divides the neural network into multiple dendritic circuits, each containing multiple synapse circuits with different RC delay lines. By segmenting the functionality across multiple specialized circuits rather than using a single complex timing mechanism, the patent achieves comprehensive coincidence detection capability while distributing the area requirement across modular units that can be efficiently packed on the chip.
Solution Approach 2:
The patent uses periodic spike trains as input signals to the neural network. The RC delay lines are designed with time constants that are optimized for detecting coincidences within specific periodic patterns. This periodic operation allows the use of simpler, smaller RC components rather than requiring complex continuous-time delay mechanisms, thereby reducing overall chip area while maintaining coincidence detection capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for effective coincidence detection and signal integration by aligning delayed spikes, achieving high detection performance with a low memory footprint.
Implementation Method 1
the first synapse circuit further comprises a first capacitor coupled to the first resistive memory element and configured to introduce the first time delay
Implementation Method 2
a first synapse circuit configured to apply a first time delay to a first input signal using a first resistive memory element and to generate a first output signal at an output of the first synapse circuit by applying a first weight to the delayed first input signal
Data Source
AI summary
The present disclosure relates to a neural network comprising a first synapse circuit (106) configured to apply a first time delay to a first input signal (READ1) using a first resistive memory element (108) and to generate a first output signal at an output of the first synapse circuit by applying a first weight to the delayed first input signal; and a second synapse circuit (106) configured to apply a second time delay, different to the first time delay, to the first input signal, or to a second input signal (READN), using a second resistive memory element (108) and to generate a second output signal at an output of the second synapse circuit by applying a second weight to the delayed second input signal.