Memory Port Modes for Dual-Port SRAM Reliability
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Solution Overview
Problem
Memory arrays, particularly dual port SRAM arrays, face errors such as write and read failures when operating at lower voltages, higher speeds, or in smaller topologies, due to charge interference between memory cells, leading to corruption of stored values.
Innovation Solution
Implementing a port mode signal to toggle the memory array between single port and dual port modes, using access control circuitry to selectively activate word-lines and bit-lines, and introducing time delays in write and read assist operations to minimize charge interference and ensure accurate data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory array operates at lower voltages and higher speeds, then productivity and speed are improved, but write and read failures increase due to charge interference between memory cells
Solution Approach 1:
The patent applies preliminary action by precharging bit-lines to a specific voltage level before memory access operations. This preparatory step ensures that when memory cells are accessed at high speeds, the bit-lines are already in the correct state to accommodate rapid charge changes, thereby preventing write and read failures caused by charge interference while maintaining high productivity
2Productivity
If dual port mode is used to access two memory cells simultaneously, then productivity is improved, but charge interference between cells increases causing errors
Solution Approach 1:
The patent applies local quality by selectively activating specific word-lines and bit-lines based on the port mode signal. When in dual port mode, only the necessary word-lines and bit-lines for each port are activated, while others remain inactive. This localized activation minimizes charge interference between memory cells accessed by different ports, allowing simultaneous access without errors
3Reliability
If write assist mechanisms are used to prevent write failures, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies feedback by implementing control circuitry that monitors the port mode signal and dynamically adjusts word-line and bit-line activations accordingly. This feedback mechanism enables write assist operations when needed (improving reliability) while keeping the control logic relatively simple through systematic decision-making based on the port mode signal
Data Source
AI summary
Various implementations described herein may refer to and may be directed to using port modes with memory. In one implementation, a memory device may include access control circuitry used to selectively activate one of a plurality of first word-lines based on first address signals from a first access port, and used to selectively activate one of a plurality of second word-lines based on assigned address signals. The access control circuitry may include address selection circuitry configured to select the assigned address signals based on a port mode signal, where the address selection circuitry selects the first address signals as the assigned address signals when the port mode signal indicates a single port mode, and where the address selection circuitry selects second address signals from a second access port as the assigned address signals when the port mode signal indicates a dual port mode.