Source-Line Voltage Boosting for Resistive Memory Leakage Reduction
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Solution Overview
Problem
Resistive memory cells face challenges with sub-threshold leakage, which degrades sense margin and increases power consumption due to the need for a negative supply rail and charge pump activation, especially in low-power applications and deeply-scaled technologies.
Innovation Solution
A leakage sensor is used to boost the Source-Line (SL) voltage above ground level, reducing sub-threshold leakage by determining the required voltage boost based on process, voltage, and temperature conditions, and utilizing a replica memory column with a negative feedback structure to control the SL voltage, thereby reducing power consumption and design complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a negative supply rail and charge pump are used to reduce sub-threshold leakage, then leakage current is reduced, but DC power consumption increases prohibitively and design complexity increases
Solution Approach 1:
The patent changes the voltage parameter of the source line from ground level to a boosted positive voltage level. By dynamically adjusting the source line voltage based on process, voltage, and temperature conditions, the invention reduces sub-threshold leakage without requiring a negative supply rail or continuously active charge pump, thereby avoiding prohibitive DC power consumption
Solution Approach 2:
The invention implements dynamic voltage boosting of the source line that adapts to varying operating conditions. The voltage boost is adjusted in real-time based on PVT conditions and memory column leakage characteristics, replacing the static negative voltage approach with a dynamic positive voltage adjustment mechanism that reduces both leakage and power consumption
2Object-generated harmful factors
If a negative supply rail and charge pump are used to reduce sub-threshold leakage, then leakage current is reduced, but design complexity increases due to high-voltage induced reliability issues
Solution Approach 1:
Instead of applying negative voltage to the source line as in conventional DRAM approaches, the patent inverts the approach by applying a boosted positive voltage to the source line. This inversion eliminates the need for negative voltage generation circuitry and high-voltage handling, thereby reducing design complexity and improving reliability
Solution Approach 2:
The invention extracts and removes the negative supply rail and associated charge pump circuitry from the memory system. By eliminating these complex high-voltage components entirely and replacing them with a simplified positive voltage boosting mechanism, the patent reduces design complexity and high-voltage induced reliability issues
3Ease of operation
If fixed voltage is applied between BL and SL nodes, then read operation is simple, but leakage current through unselected memory cells degrades sense margin
Solution Approach 1:
The patent applies different voltage conditions to different parts of the memory system: selected memory cells receive the proper voltage for reading while unselected memory cells experience a voltage differential that suppresses their leakage current. The boosted source line voltage creates local voltage conditions that reduce leakage in unselected cells without affecting the read operation of selected cells, thereby improving sense margin while maintaining operational simplicity
Data Source
AI summary
Described is an apparatus comprising a leakage tracker to track leakage of a column of resistive memory cells; and a circuit for adjusting voltage on a SourceLine (SL) of the column of resistive memory cells. Described is also an apparatus comprising: a memory array having rows and columns of resistive memory cells; a leakage tracker to track leakage current of a column of resistive memory cells associated with the memory array; and a circuit, coupled to the leakage tracker, for adaptively boosting voltage on a SL of the column of resistive memory cells during read operation.