Data Processing Circuit with Merged Write Circuits for DDR DRAM
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Solution Overview
Problem
The central region of a DDR DRAM memory has a larger circuit size due to the need for multiple write and read circuits to manage data across multiple bank groups, leading to inefficiencies in data processing.
Innovation Solution
The implementation of two write circuits with half-frequency control signals and alternating falling edges to write data into two bank groups, allowing for the merging of certain circuits and reducing the overall circuit size in the central region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple write and read circuits are used to manage data across multiple bank groups, then data access capability is improved, but circuit size in the central region increases
Solution Approach 1:
The patent merges the write circuits for the first and second bank groups into a single integrated write circuit. This write circuit includes a write input buffer that receives data from the write bus and control logic that distributes data to both bank groups, eliminating the need for separate write circuits and reducing the central region circuit size while maintaining the ability to manage data across multiple bank groups
Solution Approach 2:
The integrated write circuit is designed to serve multiple bank groups simultaneously. The control logic within the write circuit can selectively direct data to the first bank group, second bank group, or both, making the circuit universal and multi-functional, thereby reducing the overall circuit size while preserving data access capability across multiple bank groups
Data Source
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AI summary
Embodiments of the present disclosure provide a data processing circuit and a device. The circuit includes: a first bank group 301 and a second bank group 302, a write circuit 303 including one write input buffer circuit 3031, and a write circuit 304 including one write input buffer circuit 3041. The two write circuits 303 and 304 are configured to: receive stored data from a same write bus 306 by the write input buffer circuits 3031 and 3041 respectively, write the stored data into the first bank group 301 by a first read-write bus 307, and write the stored data into the second bank group 302 by a second read-write bus 308. Frequencies of control signals employed by the two write input buffer circuits 3031 and 3041 both are half of a clock frequency configured for writing the stored data by the write bus 306. In the embodiments of the present disclosure, each write circuit includes a write input buffer circuit, which may reduce the circuit size.